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  cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-01522 rev. *b revised january 08, 2016 s29gl512n S29GL256N s29gl128n 512, 256, 128 mbit, 3 v, page flash featuring 110 nm mirrorbit this product family has been retired and is not recommended for designs. for new and current designs, s29gl128s, s29gl256s, and s29gl512t supersede the s29gl128n, S29GL256N, and s29gl512n respectively . these are the factory-recommended migration paths. please refer to the s29gl-s and s29gl-t family data sheets for specifications and ordering information. distinctive characteristics architectural advantages ? single power supply operation ? 3 volt read, erase, and program operations ? enhanced versatilei/o ? control ? all input levels (address, control, and dq input levels) and outputs are determined by voltage on v io input. v io range is 1.65 to v cc ? manufactured on 110 nm mirrorbit process technology ? secured silicon sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer ? flexible sector architecture ? s29gl512n: five hundred twelve 64 kword (128 kbyte) sectors ? S29GL256N: two hundred fifty-six 64 kword (128 kbyte) sectors ? s29gl128n: one hundred twenty-eight 64 kword (128 kbyte) sectors ? compatibility with jedec standards ? provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection ? 100,000 erase cycles per sector typical ? 20-year data retention typical performance characteristics ? high performance ? 90 ns access time (s29gl128n, S29GL256N) ? 100 ns (s29gl512n) ? 8-word/16-byte page read buffer ? 25 ns page read times ? 16-word/32-byte write buffer reduces overall programming time for multiple-word updates ? low power consumption (typical values at 3.0 v, 5 mhz) ? 25 ma typical active read current; ? 50 ma typical erase/program current ? 1 a typical standby mode current ? package options ? 56-pin tsop ? 64-ball fortified bga software & hard ware features ? software features ? program suspend and resume: read other sectors before programming operation is completed ? erase suspend and resume: read/program other sectors before an erase operation is completed ? data# polling and toggle bits provide status ? unlock bypass program command reduces overall multiple-word programming time ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices ? hardware features ? advanced sector protection ? wp#/acc input accelerates programming time (when high voltage is applied) for greater throughput during system production. protects first or last sector regardless of sector protection settings ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completion product availability table density init. access v cc availability 512 mb 110 ns full now 100 ns full now 256 mb 110 ns full now 100 ns full now 90 ns regulated now 128 mb 110 ns full now 100 ns full now 90 ns regulated now not recommended for new design
document number: 002-01522 rev. *b page 2 of 92 s29gl512n S29GL256N s29gl128n general description the s29gl512/256/128n family of devices are 3.0v single power flash memory manufactured using 110 nm ? mirrorbit technology. the s29gl512n is a 512 mbit, organized as 33,554,432 words or 67,108,864 bytes. the S29GL256N is a 256 mbit, organized as 16,777,216 words or 33,554,432 bytes. the s29gl128n is a 128 mbit, organized as 8,388,608 words or 16,777,216 bytes. the devices have a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the byte# input. the device can b e programmed either in th e host system or in st andard eprom programmers. access times as fast as 90 ns (s29gl128n, S29GL256N), 100 ns (s 29gl512n) are available. note that each access time has a specific operating voltage range (v cc ) and an i/o voltage range (v io ), as specified in the product selector guide on page 4 and the ordering information on page 9 . the devices are offered in a 56-pin tsop or 64-ball fortified bga package. each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high- voltage accelerated program ( wp#/ acc) input provides shorter programming times th rough increased current. this feature is intended to facilita te factory throughput du ring system production, but may also be used in the field if desired. the devices are entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the device using standard micropr ocessor write timing. write cycles also internally latch addr esses and data needed for the programming and erase operations. the sector erase architecture allows memory sectors to be erased and reprog rammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase operation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to determine whether the operation is complete. to facilitate programming, an unlock bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. the enhanced versatilei/o? (v io ) control allows the host system to set the voltage levels th at the device generat es and tolerates on all input levels (address, chip control, and dq input le vels) to the same voltage level that is asserted on the v io pin. this allows the device to operate in a 1.8 v or 3 v system environment as required. hardware data protection measures include a low v cc detector that automatically inhi bits write operations during power transitions. persistent sect or protection provides in-system, command-enabled protecti on of any combination of sectors using a single power supply at v cc . password sector protection prevents unauthorized write and eras e operations in any combination of sectors through a user-defined 64-bit password. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then co mplete the erase operation. the program suspend/program resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets t he device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circui try. a system reset would thus also reset the device, enabling the host system to read boot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the secured silicon sector provides a 128-word/256-byte area for code or data that can be permanently protected. once this sector is protected, no further changes within the sector can occur. the write protect (wp#/acc) feature protects the first or last sect or by asserting a logic low on the wp# pin. mirrorbit flash technology combines years of flash memory manufa cturing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assiste d erase. the data is programmed using hot electron injection. not recommended for new design
document number: 002-01522 rev. *b page 3 of 92 s29gl512n S29GL256N s29gl128n contents 1. product selector guide ............................................... 4 1.1 s29gl512n ................ .......................................... ......... 4 1.2 S29GL256N, s29gl128n ........... ............................ ...... 4 2. block diagram .............................................................. 5 3. connection diagrams .................................................. 6 3.1 special package handling inst ructions.......................... 7 4. pin description ............................................................. 7 5. logic symbol ............................................................... 7 6. ordering information ................................................... 9 7. device bus operations .............................................. 10 7.1 word/byte configuration.............................................. 10 7.2 versatileio tm (v io ) control .......................................... 10 7.3 requirements for reading array data......................... 10 7.4 writing commands/command sequences.................. 11 7.5 standby mode.............................................................. 11 7.6 automatic sleep mode................................................. 12 7.7 reset#: hardware reset pin............. .............. .......... 12 7.8 output disable mode ................................................... 13 7.9 autoselect mode .......................................................... 34 7.10 sector protection ......................................................... 34 7.11 advanced sector protection ........................................ 35 7.12 lock register ............................................................... 35 7.13 persistent sector protection ........................................ 36 7.14 persistent protection mode lock bit ............................ 37 7.15 password sector protection......................................... 38 7.16 password and password protection mode lock bit .... 38 7.17 64-bit password ........................................................... 38 7.18 persistent protection bit lock (ppb lock bit) .............. 38 7.19 secured silicon sector flash memory region ............ 39 7.20 write protect (wp#) ..................................................... 40 7.21 hardware data protection............................................ 40 8. common flash memory interface (cfi) ................... 40 9. command definitions ................................................ 43 9.1 reading array data ..................................................... 43 9.2 reset command .......................................................... 43 9.3 autoselect command sequence ................................. 44 9.4 enter secured silicon sector/exit secured silicon sector command sequence........... ...................... ....... 44 9.5 word program command sequence........................... 44 9.6 program suspend/program resume command sequence..................................................................... 48 9.7 chip erase command sequence ......................... ....... 49 9.8 sector erase command sequence ............................. 50 9.9 erase suspend/erase resume commands ... ............. 51 9.10 lock register command set definitions ..................... 51 9.11 password protection comm and set definitions .......... 52 9.12 non-volatile sector protection command set definitions .................................................................... 52 9.13 global volatile sector protection freeze command set............................................................................... 53 9.14 volatile sector protection command set..................... 53 9.15 secured silicon sector en try command........ ............... 54 9.16 secured silicon sector exit command ......................... 54 9.17 command definitions.............. ...................................... 54 10. write operation status ............................................... 59 10.1 dq7: data# polling ....................................................... 59 10.2 ry/by#: ready/busy#.................................................. 60 10.3 dq6: toggle bit i .......................................................... 60 10.4 dq2: toggle bit ii ......................................................... 62 10.5 reading toggle bits dq6/dq2. ............. .............. ......... 62 10.6 dq5: exceeded timing limits ...................................... 62 10.7 dq3: sector erase timer...... ........................................ 63 10.8 dq1: write-to-buffer abort............................................ 63 11. absolute maximum ratings ....................................... 64 12. operating ranges ....................................................... 65 13. dc characteristics ...................................................... 65 13.1 cmos compatible ........................................................ 65 14. test conditions ........................................................... 66 14.1 key to switching waveforms ........................................ 67 15. ac characteristics ...................................................... 68 15.1 read-only operations .......... ................................. ....... 68 15.2 hardware reset (reset#)..... ............................. ......... 69 15.3 erase and program operations .................................... 71 15.4 alternate ce# controlled erase and program operations: s29gl128n, S29GL256N, s29g l512n........... ............ 75 16. erase and programming performance ..................... 77 17. tsop pin and bga package capacitance ................ 77 1 8. physical dimensions .................................................. 78 18.1 ts056?56-pin standard thin small outline package (tsop).......................................................................... 78 18.2 laa064?64-ball fortified ball grid array (fbga)....... 79 19. advance information on s29gl-p hardware reset (reset#) and power-up sequence ................................... 80 20. advance information on s29gl-r 65 nm mirrorbit ..... hardware reset (reset#) and power-u p sequence ....... 82 21. document history page ............................................. 84 not recommended for new design
document number: 002-01522 rev. *b page 4 of 92 s29gl512n S29GL256N s29gl128n 1. product selector guide 1.1 s29gl512n 1.2 S29GL256N, s29gl128n part number s29gl512n speed option v cc = 2.7?3.6 v v io = 2.7?3.6 v 10 11 v io = 1.65?3.6 v 11 max. access time (ns) 100 110 110 max. ce# access time (ns) 100 110 110 max. page access time (ns) 25 25 30 max. oe# access time (ns) 25 35 35 part number S29GL256N, s29gl128n speed option v cc = 2.7?3.6 v v io = 2.7?3.6 v 10 11 v io = 1.65?3.6 v 11 v cc = regulated (3.0?3.6 v) v io = regulated (3.0?3.6 v) 90 max. access time (ns) 90 100 110 110 max. ce# access time (ns) 90 100 110 110 max. page access time (ns) 25 25 25 30 max. oe# access time (ns) 25 25 35 35 not recommended for new design
document number: 002-01522 rev. *b page 5 of 92 s29gl512n S29GL256N s29gl128n 2. block diagram note ** a max gl512n = a24, a max gl256n = a23, a max gl128n = a22 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss v io we# wp#/acc byte# ce# oe# stb stb dq15 ? dq0 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a max **?a0 not recommended for new design
document number: 002-01522 rev. *b page 6 of 92 s29gl512n S29GL256N s29gl128n 3. connection diagrams figure 3.1 56-pin standard tsop figure 3.2 64-ball fortified bga notes 1. ball c8 is nc on s29gl128n 2. ball f8 is nc on S29GL256N and s29gl128n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a23 a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 a24 nc a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 23 24 25 26 27 28 a4 a3 a2 a1 nc nc 34 33 32 31 30 29 oe# v ss ce# a0 nc v io nc for S29GL256N and s29gl128n nc for s29gl128n a2 c2 d2 e2 f2 g2 h2 a3 c3 d3 e3 f3 g3 h3 a4 c4 d4 e4 f4 g4 h4 a5 c5 d5 e5 f5 g5 h5 a6 c6 d6 e6 f6 g6 h6 a7 c7 d7 e7 f7 g7 h7 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 reset# we# dq11 dq3 dq10 dq2 a20 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 a1 c1 d1 e1 f1 g1 h1 nc nc v io nc nc nc nc nc a8 c8 b2 b3 b4 b5 b6 b7 b1 b8 d8 e8 f8 g8 h8 nc nc a24 2 v ss v io a23 1 a22 nc top view, balls facing down not recommended for new design
document number: 002-01522 rev. *b page 7 of 92 s29gl512n S29GL256N s29gl128n 3.1 special package handling instructions special handling is required for flash memory products in mold ed packages (tsop, bga). the pack age and/or data integrity may be compromised if the package body is exposed to temperatures above 150 ? c for prolonged periods of time. 4. pin description 5. logic symbol figure 5.1 s29gl512n a24?a0 25 address inputs (512 mb) a23?a0 24 address inputs (256 mb) a22?a0 23 address inputs (128 mb) dq14?dq0 15 data inputs/outputs dq15/a-1 dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# chip enable input oe# output enable input we# write enable input wp#/acc hardware write protect input; acceleration input reset# hardware reset pin input byte# selects 8-bit or 16-bit mode ry/by# ready/busy output v cc 3.0 volt-only single power supply (see product selector guide on page 4 for speed options and voltage supply tolerances) v io output buffer power v ss device ground nc pin not connected internally 25 16 or 8 dq15?dq0 (a-1) a24?a0 ce# oe# we# reset# ry/by# wp#/acc v io byte# not recommended for new design
document number: 002-01522 rev. *b page 8 of 92 s29gl512n S29GL256N s29gl128n figure 5.2 S29GL256N figure 5.3 s29gl128n this product family has been retired and is not recommended fo r designs. for new and current designs, s29gl128p, s29gl256p, and s29gl512p supersede s29gl128n, s2 9gl256n, and s29gl512n respectively. these are the factory-recommended migration paths. please refer to the s29gl-p family dat a sheets for specifications and ordering information. 24 16 or 8 dq15?dq0 (a-1) a23?a0 ce# oe# we# reset# ry/by# wp#/acc v io byte# 23 16 or 8 dq15?dq0 (a-1) a22?a0 ce# oe# we# reset# ry/by# wp#/acc v io byte# not recommended for new design
document number: 002-01522 rev. *b page 9 of 92 s29gl512n S29GL256N s29gl128n 6. ordering information the ordering part number is formed by a valid combination of the following: valid combinations valid combinations list configurations planne d to be supported in volume for this device. consult your local sales office to co nfirm availability of specific valid combinations and to check on newly released combinations. notes 1. type 0 is standard. specify other options as required. tsop can be packed in types 0 and 3; bga can be packed in types 0, 2, 3. 2. tsop package marking omits packing type designator from ordering part number. 3. bga package marking omits leading ?s29? and packing type designator from ordering part number. 4. contact a local sales representative for availability. s29gl512n 11 f f i 01 0 packing type 0 = tray (standard; see note 1 ) 2 = 7? tape and reel 3 = 13? tape and reel model number (v io range, protection when wp# =v il ) 01 = v io = v cc = 2.7 to 3.6 v, highest address sector protected 02 = v io = v cc = 2.7 to 3.6 v, lowest address sector protected v1 = v io = 1.65 to 3.6 v, v cc = 2.7 to 3.6 v, highest address sector protected v2 = v io = 1.65 to 3.6 v, v cc = 2.7 to 3.6 v, lowest address sector protected r1 = v io = v cc = 3.0 to 3.6 v, highest address sector protected r2 = v io = v cc = 3.0 to 3.6 v, lowest address sector protected temperature range i = industrial (?40c to +85c) package materials set a = snpb f = pb-free (recommended) package type t = thin small outline package (tsop) standard pinout (ts056) f = fortified ball grid array, 1.0 mm pitch package (laa064) speed option 90 = 90 ns (note 4) 10 = 100 ns (note 4) 11 = 110 ns (recommended) device number/description s29gl128n, S29GL256N, s29gl512n 3.0 volt-only, 512 megabit (32 m x 16-bit/64 m x 8-bit) page-mode flash memory manufactured on 110 nm mirrorbit process technology s29gl-n valid combinations base part number speed (ns) package temperature model number packing type s29gl128n 90 ta, tf (note 2) ; fa, ff (note 3) i r1, r2 0, 2, 3 (note 1) 10, 11 01, 02 11 v1, v2 S29GL256N 90 ta, tf (note 2) ; fa, ff (note 3) i r1, r2 0, 2, 3 (note 1) 10, 11 01, 02 11 v1, v2 s29gl512n 10, 11 ta, tf (note 2) ; fa, ff (note 3) i 01, 02 0, 2, 3 (note 1) 11 v1, v2 not recommended for new design
document number: 002-01522 rev. *b page 10 of 92 s29gl512n S29GL256N s29gl128n 7. device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addre ssable memory location. the register is a latch used to store th e commands, along with the address and data information needed to ex ecute the command. the contents of the register serve as inputs to the internal state machine. the state ma chine outputs dictate the function of the device. table lists the device bus operations, the inputs and control levels they require, and the resulting output. t he following subsections describe each of th ese operations in further detail. legend l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes 1. addresses are amax:a0 in word mode; a max :a-1 in byte mode. sector addresses are a max :a16 in both modes. 2. if wp# = v il , the first or last sector group remains protected. if wp# = v ih , the first or last sector is protected or unpro tected as determined by the method described in ?write protect (wp#)?. all sectors are unprotected when shipped from the factory (the secured silicon sector may be factory pro tected depending on version ordered.) 3. d in or d out as required by command sequence, data pol ling, or sector protect algorithm (see figure 9.2 on page 48 , figure 9.4 on page 50 , and figure 10.1 on page 60 ). 7.1 word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at l ogic ?1?, the device is in word configuration, dq 0?dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte co nfiguration, and only data i/o pi ns dq0?dq7 are active and contro lled by ce# and oe#. the data i/o pins dq8?dq14 ar e tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function . 7.2 versatileio tm (v io ) control the versatileio tm (v io ) control allows the host system to set the voltage leve ls that the device generates and tolerates on ce# and dq i/os to the same voltage level that is asserted on v io . see ordering information for v io options on this device. for example, a v i/o of 1.65?3.6 volts allows for i/o at the 1.8 or 3 volt levels, driving and receiv ing signals to and from other 1.8 or 3 v devices on the same data bus. 7.3 requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array da ta to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content o ccurs during the power transition. no command is necessary in this mode to obtain ar ray data. standard microprocessor read cycles that assert valid addre sses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. device bus operations operation ce# oe# we# reset# wp#/acc addresses (note 1) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read l l h h x a in d out d out dq8?dq14 = high-z, dq15 = a-1 write (program/erase) l h l h (note 2) a in (note 3) (note 3) accelerated program l h l h v hh a in (note 3) (note 3) standby v cc 0.3 v xx v cc 0.3 v h x high-z high-z high-z output disable l h h h x x high-z high-z high-z reset x x x l x x high-z high-z high-z not recommended for new design
document number: 002-01522 rev. *b page 11 of 92 s29gl512n S29GL256N s29gl128n see reading array data on page 43 for more information. refer to the ac read-only operations tabl e for timing specifications and to figure 15.1 on page 68 for the timing diagram. refer to the dc characteristics table for the active current specification on reading array data. 7.3.1 page mode read the device is capable of fast page mode read and is compatib le with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the pag e size of the device is 8 words/16 bytes. the appropriate p age is selected by the higher address bits a(max)?a3. address bits a 2?a0 in word mode (a2?a-1 in byte mode) determine the specific word within a page. this is an asynchronous operation; the microprocessor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce# is de-asserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode accesses are obtained by keepi ng the ?read-page addresses? constant and changing the ?intra-read page? addresses. 7.4 writing commands/command sequences to write a command or command sequence (whi ch includes programming data to the de vice and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a word or byte, instead of four. the ?word program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, mu ltiple sectors, or the entire device. table on page 13 , table on page 31 , and table on page 34 indicate the address space that each sector occupies. refer to the dc characteristics table for the active current spec ification for the write mode. the ac characteristics section c ontains timing specification tables and timi ng diagrams for write operations. 7.4.1 write buffer write buffer programming allows th e system write to a maximum of 16 words/32 byte s in one programming ope ration. this results i n faster effective programming time than the standard programming algorithms. see write buffer on page 11 for more information. 7.4.2 accelerated program operation the device offers accelerated program operati ons through the acc function. this is one of two functions provided by the wp#/acc pin. this function is primarily intended to allo w faster manufacturing th roughput at the factory. if the system asserts v hh on this pin, the device autom atically enters the aforementioned unlock by pass mode, temporarily unprotects any protected sector groups, a nd uses the higher voltage on the pin to reduce the time required for program operatio ns. the system would use a two-cycle progra m command sequence as re quired by the unlock by pass mode. removing v hh from the wp#/acc pin returns the device to normal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. wp# has an internal pull-up; when unconnected, wp# is at v ih . 7.4.3 autoselect functions if the system writes the autoselect command sequence, the device enters the autose lect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the autoselect mode on page 34 and autoselect command sequence on page 44 , for more information. 7.5 standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and t he outputs are placed in the high impedanc e state, independent of the oe# input. the device enters the cmos stan dby mode when the ce # and reset# pins are both held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v io 0.3 v, the device is in the standby mode, not recommended for new design
document number: 002-01522 rev. *b page 12 of 92 s29gl512n S29GL256N s29gl128n but the standby current is greater. the de vice requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or programming, t he device draws active current until the operation is completed. refer to dc characteristics on page 65 for the standby current specification. 7.6 automatic sleep mode the automatic sleep mode minimizes flash device energy cons umption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep m ode, output data is latched and always available to the system. refer to dc characteristics on page 65 for the automatic sleep mo de current specification. 7.7 reset#: hardware reset pin the reset# pin provides a hardware method of resett ing the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the reset# pulse. the device also resets the intern al state machine to reading array data. t he operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure dat a integrity. current is reduced for the du ration of the reset # pulse. when reset # is held at v ss 0.3 v, the device draws cmos standby current (i cc5 ). if reset# is held at v il but not within v ss 0.3 v, the standby current is greater. the reset# pin may be tied to the system rese t circuitry. a system reset would thus also reset t he flash memory , enabling the system to read the boot-up firm ware from the flash memory. refer to the ac charac teristics tables for r eset# parameters and to figure 15.3 on page 70 for the timing diagram. not recommended for new design
document number: 002-01522 rev. *b page 13 of 92 s29gl512n S29GL256N s29gl128n 7.8 output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. sector address table?s29gl512n (sheet 1 of 12) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 0 0 0 0 0 0 0 0 0 128/64 0000000?001ffff 0000000?000ffff sa1 0 0 0 0 0 0 0 0 1 128/64 0020000?003ffff 0010000?001ffff sa2 0 0 0 0 0 0 0 1 0 128/64 0040000?005ffff 0020000?002ffff sa3 0 0 0 0 0 0 0 1 1 128/64 0060000?007ffff 0030000?003ffff sa4 0 0 0 0 0 0 1 0 0 128/64 0080000?009ffff 0040000?004ffff sa5 0 0 0 0 0 0 1 0 1 128/64 00a0000?00bffff 0050000?005ffff sa6 0 0 0 0 0 0 1 1 0 128/64 00c0000?00dffff 0060000?006ffff sa7 0 0 0 0 0 0 1 1 1 128/64 00e0000?00fffff 0070000?007ffff sa8 0 0 0 0 0 1 0 0 0 128/64 0100000?011ffff 0080000?008ffff sa9 0 0 0 0 0 1 0 0 1 128/64 0120000?013ffff 0090000?009ffff sa10 0 0 0 0 0 1 0 1 0 128/64 0140000?015ffff 00a0000?00affff sa11 0 0 0 0 0 1 0 1 1 128/64 0160000?017ffff 00b0000?00bffff sa12 0 0 0 0 0 1 1 0 0 128/64 0180000?019ffff 00c0000?00cffff sa13 0 0 0 0 0 1 1 0 1 128/64 01a0000?01bffff 00d0000?00dffff sa14 0 0 0 0 0 1 1 1 0 128/64 01c0000?01dffff 00e0000?00effff sa15 0 0 0 0 0 1 1 1 1 128/64 01e0000?01fffff 00f0000?00fffff sa16 0 0 0 0 1 0 0 0 0 128/64 0200000?021ffff 0100000?010ffff sa17 0 0 0 0 1 0 0 0 1 128/64 0220000?023ffff 0110000?011ffff sa18 0 0 0 0 1 0 0 1 0 128/64 0240000?025ffff 0120000?012ffff sa19 0 0 0 0 1 0 0 1 1 128/64 0260000?027ffff 0130000?013ffff sa20 0 0 0 0 1 0 1 0 0 128/64 0280000?029ffff 0140000?014ffff sa21 0 0 0 0 1 0 1 0 1 128/64 02a0000?02bffff 0150000?015ffff sa22 0 0 0 0 1 0 1 1 0 128/64 02c0000?02dffff 0160000?016ffff sa23 0 0 0 0 1 0 1 1 1 128/64 02e0000?02fffff 0170000?017ffff sa24 0 0 0 0 1 1 0 0 0 128/64 0300000?031ffff 0180000?018ffff sa25 0 0 0 0 1 1 0 0 1 128/64 0320000?033ffff 0190000?019ffff sa26 0 0 0 0 1 1 0 1 0 128/64 0340000?035ffff 01a0000?01affff sa27 0 0 0 0 1 1 0 1 1 128/64 0360000?037ffff 01b0000?01bffff sa28 0 0 0 0 1 1 1 0 0 128/64 0380000?039ffff 01c0000?01cffff sa29 0 0 0 0 1 1 1 0 1 128/64 03a0000?03bffff 01d0000?01dffff sa30 0 0 0 0 1 1 1 1 0 128/64 03c0000?03dffff 01e0000?01effff sa31 0 0 0 0 1 1 1 1 1 128/64 03e0000?0efffff 01f0000?01fffff sa32 0 0 0 1 0 0 0 0 0 128/64 0400000?041ffff 0200000?020ffff sa33 0 0 0 1 0 0 0 0 1 128/64 0420000?043ffff 0210000?021ffff sa34 0 0 0 1 0 0 0 1 0 128/64 0440000?045ffff 0220000?022ffff sa35 0 0 0 1 0 0 0 1 1 128/64 0460000?047ffff 0230000?023ffff sa36 0 0 0 1 0 0 1 0 0 128/64 0480000?049ffff 0240000?024ffff sa37 0 0 0 1 0 0 1 0 1 128/64 04a0000?04bffff 0250000?025ffff sa38 0 0 0 1 0 0 1 1 0 128/64 04c0000?04dffff 0260000?026ffff sa39 0 0 0 1 0 0 1 1 1 128/64 04e0000?04fffff 0270000?027ffff sa40 0 0 0 1 0 1 0 0 0 128/64 0500000?051ffff 0280000?028ffff sa41 0 0 0 1 0 1 0 0 1 128/64 0520000?053ffff 0290000?029ffff not recommended for new design
document number: 002-01522 rev. *b page 14 of 92 s29gl512n S29GL256N s29gl128n sa42 0 0 0 1 0 1 0 1 0 128/64 0540000?055ffff 02a0000?02affff sa43 0 0 0 1 0 1 0 1 1 128/64 0560000?057ffff 02b0000?02bffff sa44 0 0 0 1 0 1 1 0 0 128/64 0580000?059ffff 02c0000?02cffff sa45 0 0 0 1 0 1 1 0 1 128/64 05a0000?05bffff 02d0000?02dffff sa46 0 0 0 1 0 1 1 1 0 128/64 05c0000?05dffff 02e0000?02effff sa47 0 0 0 1 0 1 1 1 1 128/64 05e0000?05fffff 02f0000?02fffff sa48 0 0 0 1 1 0 0 0 0 128/64 0600000?061ffff 0300000?030ffff sa49 0 0 0 1 1 0 0 0 1 128/64 0620000?063ffff 0310000?031ffff sa50 0 0 0 1 1 0 0 1 0 128/64 0640000?065ffff 0320000?032ffff sa51 0 0 0 1 1 0 0 1 1 128/64 0660000?067ffff 0330000?033ffff sa52 0 0 0 1 1 0 1 0 0 128/64 0680000?069ffff 0340000?034ffff sa53 0 0 0 1 1 0 1 0 1 128/64 06a0000?06bffff 0350000?035ffff sa54 0 0 0 1 1 0 1 1 0 128/64 06c0000?06dffff 0360000?036ffff sa55 0 0 0 1 1 0 1 1 1 128/64 06e0000?06fffff 0370000?037ffff sa56 0 0 0 1 1 1 0 0 0 128/64 0700000?071ffff 0380000?038ffff sa57 0 0 0 1 1 1 0 0 1 128/64 0720000?073ffff 0390000?039ffff sa58 0 0 0 1 1 1 0 1 0 128/64 0740000?075ffff 03a0000?03affff sa59 0 0 0 1 1 1 0 1 1 128/64 0760000?077ffff 03b0000?03bffff sa60 0 0 0 1 1 1 1 0 0 128/64 0780000?079ffff 03c0000?03cffff sa61 0 0 0 1 1 1 1 0 1 128/64 07a0000?07bffff 03d0000?03dffff sa62 0 0 0 1 1 1 1 1 0 128/64 07c0000?07dffff 03e0000?03effff sa63 0 0 0 1 1 1 1 1 1 128/64 07e0000?07fffff 03f0000?03fffff sa64 0 0 1 0 0 0 0 0 0 128/64 0800000?081ffff 0400000?040ffff sa65 0 0 1 0 0 0 0 0 1 128/64 0820000?083ffff 0410000?041ffff sa66 0 0 1 0 0 0 0 1 0 128/64 0840000?085ffff 0420000?042ffff sa67 0 0 1 0 0 0 0 1 1 128/64 0860000?087ffff 0430000?043ffff sa68 0 0 1 0 0 0 1 0 0 128/64 0880000?089ffff 0440000?044ffff sa69 0 0 1 0 0 0 1 0 1 128/64 08a0000?08bffff 0450000?045ffff sa70 0 0 1 0 0 0 1 1 0 128/64 08c0000?08dffff 0460000?046ffff sa71 0 0 1 0 0 0 1 1 1 128/64 08e0000?08fffff 0470000?047ffff sa72 0 0 1 0 0 1 0 0 0 128/64 0900000?091ffff 0480000?048ffff sa73 0 0 1 0 0 1 0 0 1 128/64 0920000?093ffff 0490000?049ffff sa74 0 0 1 0 0 1 0 1 0 128/64 0940000?095ffff 04a0000?04affff sa75 0 0 1 0 0 1 0 1 1 128/64 0960000?097ffff 04b0000?04bffff sa76 0 0 1 0 0 1 1 0 0 128/64 0980000?099ffff 04c0000?04cffff sa77 0 0 1 0 0 1 1 0 1 128/64 09a0000?09bffff 04d0000?04dffff sa78 0 0 1 0 0 1 1 1 0 128/64 09c0000?09dffff 04e0000?04effff sa79 0 0 1 0 0 1 1 1 1 128/64 09e0000?09fffff 04f0000?04fffff sa80 0 0 1 0 1 0 0 0 0 128/64 0a00000?0a1ffff 0500000?050ffff sa81 0 0 1 0 1 0 0 0 1 128/64 0a20000?0a3ffff 0510000?051ffff sa82 0 0 1 0 1 0 0 1 0 128/64 0a40000?0a5ffff 0520000?052ffff sa83 0 0 1 0 1 0 0 1 1 128/64 0a60000?0a7ffff 0530000?053ffff sa84 0 0 1 0 1 0 1 0 0 128/64 0a80000?0a9ffff 0540000?054ffff sa85 0 0 1 0 1 0 1 0 1 128/64 0aa0000?0abffff 0550000?055ffff sa86 0 0 1 0 1 0 1 1 0 128/64 0ac0000?0adffff 0560000?056ffff sector address table?s29gl512n (sheet 2 of 12) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 15 of 92 s29gl512n S29GL256N s29gl128n sa87 0 0 1 0 1 0 1 1 1 128/64 0ae0000?0afffff 0570000?057ffff sa88 0 0 1 0 1 1 0 0 0 128/64 0b00000?0b1ffff 0580000?058ffff sa89 0 0 1 0 1 1 0 0 1 128/64 0b20000?0b3ffff 0590000?059ffff sa90 0 0 1 0 1 1 0 1 0 128/64 0b40000?0b5ffff 05a0000?05affff sa91 0 0 1 0 1 1 0 1 1 128/64 0b60000?0b7ffff 05b0000?05bffff sa92 0 0 1 0 1 1 1 0 0 128/64 0b80000?0b9ffff 05c0000?05cffff sa93 0 0 1 0 1 1 1 0 1 128/64 0ba0000?0bbffff 05d0000?05dffff sa94 0 0 1 0 1 1 1 1 0 128/64 0bc0000?0bdffff 05e0000?05effff sa95 0 0 1 0 1 1 1 1 1 128/64 0be0000?0bfffff 05f0000?05fffff sa96 0 0 1 1 0 0 0 0 0 128/64 0c00000?0c1ffff 0600000?060ffff sa97 0 0 1 1 0 0 0 0 1 128/64 0c20000?0c3ffff 0610000?061ffff sa98 0 0 1 1 0 0 0 1 0 128/64 0c40000?0c5ffff 0620000?062ffff sa99 0 0 1 1 0 0 0 1 1 128/64 0c60000?0c7ffff 0630000?063ffff sa100 0 0 1 1 0 0 1 0 0 128/64 0c80000?0c9ffff 0640000?064ffff sa101 0 0 1 1 0 0 1 0 1 128/64 0ca0000?0cbffff 0650000?065ffff sa102 0 0 1 1 0 0 1 1 0 128/64 0cc0000?0cdffff 0660000?066ffff sa103 0 0 1 1 0 0 1 1 1 128/64 0ce0000?0cfffff 0670000?067ffff sa104 0 0 1 1 0 1 0 0 0 128/64 0d00000?0d1ffff 0680000?068ffff sa105 0 0 1 1 0 1 0 0 1 128/64 0d20000?0d3ffff 0690000?069ffff sa106 0 0 1 1 0 1 0 1 0 128/64 0d40000?0d5ffff 06a0000?06affff sa107 0 0 1 1 0 1 0 1 1 128/64 0d60000?0d7ffff 06b0000?06bffff sa108 0 0 1 1 0 1 1 0 0 128/64 0d80000?0d9ffff 06c0000?06cffff sa109 0 0 1 1 0 1 1 0 1 128/64 0da0000?0dbffff 06d0000?06dffff sa110 0 0 1 1 0 1 1 1 0 128/64 0dc0000?0ddffff 06e0000?06effff sa111 0 0 1 1 0 1 1 1 1 128/64 0de0000?0dfffff 06f0000?06fffff sa112 0 0 1 1 1 0 0 0 0 128/64 0e00000?0e1ffff 0700000?070ffff sa113 0 0 1 1 1 0 0 0 1 128/64 0e20000?0e3ffff 0710000?071ffff sa114 0 0 1 1 1 0 0 1 0 128/64 0e40000?0e5ffff 0720000?072ffff sa115 0 0 1 1 1 0 0 1 1 128/64 0e60000?0e7ffff 0730000?073ffff sa116 0 0 1 1 1 0 1 0 0 128/64 0e80000?0e9ffff 0740000?074ffff sa117 0 0 1 1 1 0 1 0 1 128/64 0ea0000?0ebffff 0750000?075ffff sa118 0 0 1 1 1 0 1 1 0 128/64 0ec0000?0edffff 0760000?076ffff sa119 0 0 1 1 1 0 1 1 1 128/64 0ee0000?0efffff 0770000?077ffff sa120 0 0 1 1 1 1 0 0 0 128/64 0f00000?0f1ffff 0780000?078ffff sa121 0 0 1 1 1 1 0 0 1 128/64 0f20000?0f3ffff 0790000?079ffff sa122 0 0 1 1 1 1 0 1 0 128/64 0f40000?0f5ffff 07a0000?07affff sa123 0 0 1 1 1 1 0 1 1 128/64 0f60000?0f7ffff 07b0000?07bffff sa124 0 0 1 1 1 1 1 0 0 128/64 0f80000?0f9ffff 07c0000?07cffff sa125 0 0 1 1 1 1 1 0 1 128/64 0fa0000?0fbffff 07d0000?07dffff sa126 0 0 1 1 1 1 1 1 0 128/64 0fc0000?0fdffff 07e0000?07effff sa127 0 0 1 1 1 1 1 1 1 128/64 0fe0000?0ffffff 07f0000?07fffff sa128 0 1 0 0 0 0 0 0 0 128/64 1000000?101ffff 0800000?080ffff sa129 0 1 0 0 0 0 0 0 1 128/64 1020000?103ffff 0810000?081ffff sa130 0 1 0 0 0 0 0 1 0 128/64 1040000?105ffff 0820000?082ffff sa131 0 1 0 0 0 0 0 1 1 128/64 1060000?017ffff 0830000?083ffff sector address table?s29gl512n (sheet 3 of 12) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 16 of 92 s29gl512n S29GL256N s29gl128n sa132 0 1 0 0 0 0 1 0 0 128/64 1080000?109ffff 0840000?084ffff sa133 0 1 0 0 0 0 1 0 1 128/64 10a0000?10bffff 0850000?085ffff sa134 0 1 0 0 0 0 1 1 0 128/64 10c0000?10dffff 0860000?086ffff sa135 0 1 0 0 0 0 1 1 1 128/64 10e0000?10fffff 0870000?087ffff sa136 0 1 0 0 0 1 0 0 0 128/64 1100000?111ffff 0880000?088ffff sa137 0 1 0 0 0 1 0 0 1 128/64 1120000?113ffff 0890000?089ffff sa138 0 1 0 0 0 1 0 1 0 128/64 1140000?115ffff 08a0000?08affff sa139 0 1 0 0 0 1 0 1 1 128/64 1160000?117ffff 08b0000?08bffff sa140 0 1 0 0 0 1 1 0 0 128/64 1180000?119ffff 08c0000?08cffff sa141 0 1 0 0 0 1 1 0 1 128/64 11a0000?11bffff 08d0000?08dffff sa142 0 1 0 0 0 1 1 1 0 128/64 11c0000?11dffff 08e0000?08effff sa143 0 1 0 0 0 1 1 1 1 128/64 11e0000?11fffff 08f0000?08fffff sa144 0 1 0 0 1 0 0 0 0 128/64 1200000?121ffff 0900000?090ffff sa145 0 1 0 0 1 0 0 0 1 128/64 1220000?123ffff 0910000?091ffff sa146 0 1 0 0 1 0 0 1 0 128/64 1240000?125ffff 0920000?092ffff sa147 0 1 0 0 1 0 0 1 1 128/64 1260000?127ffff 0930000?093ffff sa148 0 1 0 0 1 0 1 0 0 128/64 1280000?129ffff 0940000?094ffff sa149 0 1 0 0 1 0 1 0 1 128/64 12a0000?12bffff 0950000?095ffff sa150 0 1 0 0 1 0 1 1 0 128/64 12c0000?12dffff 0960000?096ffff sa151 0 1 0 0 1 0 1 1 1 128/64 12e0000?12fffff 0970000?097ffff sa152 0 1 0 0 1 1 0 0 0 128/64 1300000?131ffff 0980000?098ffff sa153 0 1 0 0 1 1 0 0 1 128/64 1320000?133ffff 0990000?099ffff sa154 0 1 0 0 1 1 0 1 0 128/64 1340000?135ffff 09a0000?09affff sa155 0 1 0 0 1 1 0 1 1 128/64 1360000?137ffff 09b0000?09bffff sa156 0 1 0 0 1 1 1 0 0 128/64 1380000?139ffff 09c0000?09cffff sa157 0 1 0 0 1 1 1 0 1 128/64 13a0000?13bffff 09d0000?09dffff sa158 0 1 0 0 1 1 1 1 0 128/64 13c0000?13dffff 09e0000?09effff sa159 0 1 0 0 1 1 1 1 1 128/64 13e0000?13fffff 09f0000?09fffff sa160 0 1 0 1 0 0 0 0 0 128/64 1400000?141ffff 0a00000?0a0ffff sa161 0 1 0 1 0 0 0 0 1 128/64 1420000?143ffff 0a10000?0a1ffff sa162 0 1 0 1 0 0 0 1 0 128/64 1440000?145ffff 0a20000?0a2ffff sa163 0 1 0 1 0 0 0 1 1 128/64 1460000?147ffff 0a30000?0a3ffff sa164 0 1 0 1 0 0 1 0 0 128/64 1480000?149ffff 0a40000?0a4ffff sa165 0 1 0 1 0 0 1 0 1 128/64 14a0000?14bffff 0a50000?0a5ffff sa166 0 1 0 1 0 0 1 1 0 128/64 14c0000?14dffff 0a60000?0a6ffff sa167 0 1 0 1 0 0 1 1 1 128/64 14e0000?14fffff 0a70000?0a7ffff sa168 0 1 0 1 0 1 0 0 0 128/64 1500000?151ffff 0a80000?0a8ffff sa169 0 1 0 1 0 1 0 0 1 128/64 1520000?153ffff 0a90000?0a9ffff sa170 0 1 0 1 0 1 0 1 0 128/64 1540000?155ffff 0aa0000?0aaffff sa171 0 1 0 1 0 1 0 1 1 128/64 1560000?157ffff 0ab0000?0abffff sa172 0 1 0 1 0 1 1 0 0 128/64 1580000?159ffff 0ac0000?0acffff sa173 0 1 0 1 0 1 1 0 1 128/64 15a0000?15bffff 0ad0000?0adffff sa174 0 1 0 1 0 1 1 1 0 128/64 15c0000?15dffff 0ae0000?0aeffff sa175 0 1 0 1 0 1 1 1 1 128/64 15e0000?15fffff 0af0000?0afffff sa176 0 1 0 1 1 0 0 0 0 128/64 160000?161ffff 0b00000?0b0ffff sector address table?s29gl512n (sheet 4 of 12) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 17 of 92 s29gl512n S29GL256N s29gl128n sa177 0 1 0 1 1 0 0 0 1 128/64 1620000?163ffff 0b10000?0b1ffff sa178 0 1 0 1 1 0 0 1 0 128/64 1640000?165ffff 0b20000?0b2ffff sa179 0 1 0 1 1 0 0 1 1 128/64 1660000?167ffff 0b30000?0b3ffff sa180 0 1 0 1 1 0 1 0 0 128/64 1680000?169ffff 0b40000?0b4ffff sa181 0 1 0 1 1 0 1 0 1 128/64 16a0000?16bffff 0b50000?0b5ffff sa182 0 1 0 1 1 0 1 1 0 128/64 16c0000?16dffff 0b60000?0b6ffff sa183 0 1 0 1 1 0 1 1 1 128/64 16e0000?16fffff 0b70000?0b7ffff sa184 0 1 0 1 1 1 0 0 0 128/64 1700000?171ffff 0b80000?0b8ffff sa185 0 1 0 1 1 1 0 0 1 128/64 1720000?173ffff 0b90000?0b9ffff sa186 0 1 0 1 1 1 0 1 0 128/64 1740000?175ffff 0ba0000?0baffff sa187 0 1 0 1 1 1 0 1 1 128/64 1760000?177ffff 0bb0000?0bbffff sa188 0 1 0 1 1 1 1 0 0 128/64 1780000?179ffff 0bc0000?0bcffff sa189 0 1 0 1 1 1 1 0 1 128/64 17a0000?17bffff 0bd0000?0bdffff sa190 0 1 0 1 1 1 1 1 0 128/64 17c0000?17dffff 0be0000?0beffff sa191 0 1 0 1 1 1 1 1 1 128/64 17e0000?17fffff 0bf0000?0bfffff sa192 0 1 1 0 0 0 0 0 0 128/64 1800000?181ffff 0c00000?0c0ffff sa193 0 1 1 0 0 0 0 0 1 128/64 1820000?183ffff 0c10000?0c1ffff sa194 0 1 1 0 0 0 0 1 0 128/64 1840000?185ffff 0c20000?0c2ffff sa195 0 1 1 0 0 0 0 1 1 128/64 1860000?187ffff 0c30000?0c3ffff sa196 0 1 1 0 0 0 1 0 0 128/64 1880000?189ffff 0c40000?0c4ffff sa197 0 1 1 0 0 0 1 0 1 128/64 18a0000?18bffff 0c50000?0c5ffff sa198 0 1 1 0 0 0 1 1 0 128/64 18c0000?18dffff 0c60000?0c6ffff sa199 0 1 1 0 0 0 1 1 1 128/64 18e0000?18fffff 0c70000?0c7ffff sa200 0 1 1 0 0 1 0 0 0 128/64 1900000?191ffff 0c80000?0c8ffff sa201 0 1 1 0 0 1 0 0 1 128/64 1920000?193ffff 0c90000?0c9ffff sa202 0 1 1 0 0 1 0 1 0 128/64 1940000?195ffff 0ca0000?0caffff sa203 0 1 1 0 0 1 0 1 1 128/64 1960000?197ffff 0cb0000?0cbffff sa204 0 1 1 0 0 1 1 0 0 128/64 1980000?199ffff 0cc0000?0ccffff sa205 0 1 1 0 0 1 1 0 1 128/64 19a0000?19bffff 0cd0000?0cdffff sa206 0 1 1 0 0 1 1 1 0 128/64 19c0000?19dffff 0ce0000?0ceffff sa207 0 1 1 0 0 1 1 1 1 128/64 19e0000?19fffff 0cf0000?0cfffff sa208 0 1 1 0 1 0 0 0 0 128/64 1a00000?1a1ffff 0d00000?0d0ffff sa209 0 1 1 0 1 0 0 0 1 128/64 1a20000?1a3ffff 0d10000?0d1ffff sa210 0 1 1 0 1 0 0 1 0 128/64 1a40000?1a5ffff 0d20000?0d2ffff sa211 0 1 1 0 1 0 0 1 1 128/64 1a60000?1a7ffff 0d30000?0d3ffff sa212 0 1 1 0 1 0 1 0 0 128/64 1a80000?1a9ffff 0d40000?0d4ffff sa213 0 1 1 0 1 0 1 0 1 128/64 1aa0000?1abffff 0d50000?0d5ffff sa214 0 1 1 0 1 0 1 1 0 128/64 1ac0000?1adffff 0d60000?0d6ffff sa215 0 1 1 0 1 0 1 1 1 128/64 1ae0000?1afffff 0d70000?0d7ffff sa216 0 1 1 0 1 1 0 0 0 128/64 1b00000?1b1ffff 0d80000?0d8ffff sa217 0 1 1 0 1 1 0 0 1 128/64 1b20000?1b3ffff 0d90000?0d9ffff sa218 0 1 1 0 1 1 0 1 0 128/64 1b40000?1b5ffff 0da0000?0daffff sa219 0 1 1 0 1 1 0 1 1 128/64 1b60000?1b7ffff 0db0000?0dbffff sa220 0 1 1 0 1 1 1 0 0 128/64 1b80000?1b9ffff 0dc0000?0dcffff sa221 0 1 1 0 1 1 1 0 1 128/64 1ba0000?1bbffff 0dd0000?0ddffff sector address table?s29gl512n (sheet 5 of 12) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 18 of 92 s29gl512n S29GL256N s29gl128n sa222 0 1 1 0 1 1 1 1 0 128/64 1bc0000?1bdffff 0de0000?0deffff sa223 0 1 1 0 1 1 1 1 1 128/64 1be0000?1bfffff 0df0000?0dfffff sa224 0 1 1 1 0 0 0 0 0 128/64 1c00000?1c1ffff 0e00000?0e0ffff sa225 0 1 1 1 0 0 0 0 1 128/64 1c20000?1c3ffff 0e10000?0e1ffff sa226 0 1 1 1 0 0 0 1 0 128/64 1c40000?1c5ffff 0e20000?0e2ffff sa227 0 1 1 1 0 0 0 1 1 128/64 1c60000?1c7ffff 0e30000?0e3ffff sa228 0 1 1 1 0 0 1 0 0 128/64 1c80000?1c9ffff 0e40000?0e4ffff sa229 0 1 1 1 0 0 1 0 1 128/64 1ca0000?1cbffff 0e50000?0e5ffff sa230 0 1 1 1 0 0 1 1 0 128/64 1cc0000?1cdffff 0e60000?0e6ffff sa231 0 1 1 1 0 0 1 1 1 128/64 1ce0000?1cfffff 0e70000?0e7ffff sa232 0 1 1 1 0 1 0 0 0 128/64 1d00000?1d1ffff 0e80000?0e8ffff sa233 0 1 1 1 0 1 0 0 1 128/64 1d20000?1d3ffff 0e90000?0e9ffff sa234 0 1 1 1 0 1 0 1 0 128/64 1d40000?1d5ffff 0ea0000?0eaffff sa235 0 1 1 1 0 1 0 1 1 128/64 1d60000?1d7ffff 0eb0000?0ebffff sa236 0 1 1 1 0 1 1 0 0 128/64 1d80000?1d9ffff 0ec0000?0ecffff sa237 0 1 1 1 0 1 1 0 1 128/64 1da0000?1dbffff 0ed0000?0edffff sa238 0 1 1 1 0 1 1 1 0 128/64 1dc0000?1ddffff 0ee0000?0eeffff sa239 0 1 1 1 0 1 1 1 1 128/64 1de0000?1dfffff 0ef0000?0efffff sa240 0 1 1 1 1 0 0 0 0 128/64 1e00000?1e1ffff 0f00000?0f0ffff sa241 0 1 1 1 1 0 0 0 1 128/64 1e20000?1e3ffff 0f10000?0f1ffff sa242 0 1 1 1 1 0 0 1 0 128/64 1e40000?1e5ffff 0f20000?0f2ffff sa243 0 1 1 1 1 0 0 1 1 128/64 1e60000?1e7ffff 0f30000?0f3ffff sa244 0 1 1 1 1 0 1 0 0 128/64 1e80000?1e9ffff 0f40000?0f4ffff sa245 0 1 1 1 1 0 1 0 1 128/64 1ea0000?1ebffff 0f50000?0f5ffff sa246 0 1 1 1 1 0 1 1 0 128/64 1ec0000?1edffff 0f60000?0f6ffff sa247 0 1 1 1 1 0 1 1 1 128/64 1ee0000?1efffff 0f70000?0f7ffff sa248 0 1 1 1 1 1 0 0 0 128/64 1f00000?1f1ffff 0f80000?0f8ffff sa249 0 1 1 1 1 1 0 0 1 128/64 1f20000?1f3ffff 0f90000?0f9ffff sa250 0 1 1 1 1 1 0 1 0 128/64 1f40000?1f5ffff 0fa0000?0faffff sa251 0 1 1 1 1 1 0 1 1 128/64 1f60000?1f7ffff 0fb0000?0fbffff sa252 0 1 1 1 1 1 1 0 0 128/64 1f80000?1f9ffff 0fc0000?0fcffff sa253 0 1 1 1 1 1 1 0 1 128/64 1fa0000?1fbffff 0fd0000?0fdffff sa254 0 1 1 1 1 1 1 1 0 128/64 1fc0000?1fdffff 0fe0000?0feffff sa255 0 1 1 1 1 1 1 1 1 128/64 1fe0000?1ffffff 0ff0000?0ffffff sa256 1 0 0 0 0 0 0 0 0 128/64 2000000?201ffff 1000000?100ffff sa257 1 0 0 0 0 0 0 0 1 128/64 2020000?203ffff 1010000?101ffff sa258 1 0 0 0 0 0 0 1 0 128/64 2040000?205ffff 1020000?102ffff sa259 1 0 0 0 0 0 0 1 1 128/64 2060000?207ffff 1030000?103ffff sa260 1 0 0 0 0 0 1 0 0 128/64 2080000?209ffff 1040000?104ffff sa261 1 0 0 0 0 0 1 0 1 128/64 20a0000?20bffff 1050000?105ffff sa262 1 0 0 0 0 0 1 1 0 128/64 20c0000?20dffff 1060000?106ffff sa263 1 0 0 0 0 0 1 1 1 128/64 20e0000?20fffff 1070000?107ffff sa264 1 0 0 0 0 1 0 0 0 128/64 2100000?211ffff 1080000?108ffff sa265 1 0 0 0 0 1 0 0 1 128/64 2120000?213ffff 1090000?109ffff sa266 1 0 0 0 0 1 0 1 0 128/64 2140000?215ffff 10a0000?10affff sector address table?s29gl512n (sheet 6 of 12) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 19 of 92 s29gl512n S29GL256N s29gl128n sa267 1 0 0 0 0 1 0 1 1 128/64 2160000?217ffff 10b0000?10bffff sa268 1 0 0 0 0 1 1 0 0 128/64 2180000?219ffff 10c0000?10cffff sa269 1 0 0 0 0 1 1 0 1 128/64 21a0000?21bffff 10d0000?10dffff sa270 1 0 0 0 0 1 1 1 0 128/64 21c0000?21dffff 10e0000?10effff sa271 1 0 0 0 0 1 1 1 1 128/64 21e0000?21fffff 10f0000?10fffff sa272 1 0 0 0 1 0 0 0 0 128/64 2200000?221ffff 1100000?110ffff sa273 1 0 0 0 1 0 0 0 1 128/64 2220000?223ffff 1110000?111ffff sa274 1 0 0 0 1 0 0 1 0 128/64 2240000?225ffff 1120000?112ffff sa275 1 0 0 0 1 0 0 1 1 128/64 2260000?227ffff 1130000?113ffff sa276 1 0 0 0 1 0 1 0 0 128/64 2280000?229ffff 1140000?114ffff sa277 1 0 0 0 1 0 1 0 1 128/64 22a0000?22bffff 1150000?115ffff sa278 1 0 0 0 1 0 1 1 0 128/64 22c0000?22dffff 1160000?116ffff sa279 1 0 0 0 1 0 1 1 1 128/64 22e0000?22fffff 1170000?117ffff sa280 1 0 0 0 1 1 0 0 0 128/64 2300000?231ffff 1180000?118ffff sa281 1 0 0 0 1 1 0 0 1 128/64 2320000?233ffff 1190000?119ffff sa282 1 0 0 0 1 1 0 1 0 128/64 2340000?235ffff 11a0000?11affff sa283 1 0 0 0 1 1 0 1 1 128/64 2360000?237ffff 11b0000?11bffff sa284 1 0 0 0 1 1 1 0 0 128/64 2380000?239ffff 11c0000?11cffff sa285 1 0 0 0 1 1 1 0 1 128/64 23a0000?23bffff 11d0000?11dffff sa286 1 0 0 0 1 1 1 1 0 128/64 23c0000?23dffff 11e0000?11effff sa287 1 0 0 0 1 1 1 1 1 128/64 23e0000?23fffff 11f0000?11fffff sa288 1 0 0 1 0 0 0 0 0 128/64 2400000?241ffff 1200000?120ffff sa289 1 0 0 1 0 0 0 0 1 128/64 2420000?243ffff 1210000?121ffff sa290 1 0 0 1 0 0 0 1 0 128/64 2440000?245ffff 1220000?122ffff sa291 1 0 0 1 0 0 0 1 1 128/64 2460000?247ffff 1230000?123ffff sa292 1 0 0 1 0 0 1 0 0 128/64 2480000?249ffff 1240000?124ffff sa293 1 0 0 1 0 0 1 0 1 128/64 24a0000?24bffff 1250000?125ffff sa294 1 0 0 1 0 0 1 1 0 128/64 24c0000?24dffff 1260000?126ffff sa295 1 0 0 1 0 0 1 1 1 128/64 24e0000?24fffff 1270000?127ffff sa296 1 0 0 1 0 1 0 0 0 128/64 2500000?251ffff 1280000?128ffff sa297 1 0 0 1 0 1 0 0 1 128/64 2520000?253ffff 1290000?129ffff sa298 1 0 0 1 0 1 0 1 0 128/64 2540000?255ffff 12a0000?12affff sa299 1 0 0 1 0 1 0 1 1 128/64 2560000?257ffff 12b0000?12bffff sa300 1 0 0 1 0 1 1 0 0 128/64 2580000?259ffff 12c0000?12cffff sa301 1 0 0 1 0 1 1 0 1 128/64 25a0000?25bffff 12d0000?12dffff sa302 1 0 0 1 0 1 1 1 0 128/64 25c0000?25dffff 12e0000?12effff sa303 1 0 0 1 0 1 1 1 1 128/64 25e0000?25fffff 12f0000?12fffff sa304 1 0 0 1 1 0 0 0 0 128/64 2600000?261ffff 1300000?130ffff sa305 1 0 0 1 1 0 0 0 1 128/64 2620000?263ffff 1310000?131ffff sa306 1 0 0 1 1 0 0 1 0 128/64 2640000?265ffff 1320000?132ffff sa307 1 0 0 1 1 0 0 1 1 128/64 2660000?267ffff 1330000?133ffff sa308 1 0 0 1 1 0 1 0 0 128/64 2680000?269ffff 1340000?134ffff sa309 1 0 0 1 1 0 1 0 1 128/64 26a0000?26bffff 1350000?135ffff sa310 1 0 0 1 1 0 1 1 0 128/64 26c0000?26dffff 1360000?136ffff sa311 1 0 0 1 1 0 1 1 1 128/64 26e0000?26fffff 1370000?137ffff sector address table?s29gl512n (sheet 7 of 12) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 20 of 92 s29gl512n S29GL256N s29gl128n sa312 1 0 0 1 1 1 0 0 0 128/64 2700000?271ffff 1380000?138ffff sa313 1 0 0 1 1 1 0 0 1 128/64 2720000?273ffff 1390000?139ffff sa314 1 0 0 1 1 1 0 1 0 128/64 2740000?275ffff 13a0000?13affff sa315 1 0 0 1 1 1 0 1 1 128/64 2760000?277ffff 13b0000?13bffff sa316 1 0 0 1 1 1 1 0 0 128/64 2780000?279ffff 13c0000?13cffff sa317 1 0 0 1 1 1 1 0 1 128/64 27a0000?27bffff 13d0000?13dffff sa318 1 0 0 1 1 1 1 1 0 128/64 27c0000?27dffff 13e0000?13effff sa319 1 0 0 1 1 1 1 1 1 128/64 27e0000?27fffff 13f0000?13fffff sa320 1 0 1 0 0 0 0 0 0 128/64 2800000?281ffff 1400000?140ffff sa321 1 0 1 0 0 0 0 0 1 128/64 2820000?283ffff 1410000?141ffff sa322 1 0 1 0 0 0 0 1 0 128/64 2840000?285ffff 1420000?142ffff sa323 1 0 1 0 0 0 0 1 1 128/64 2860000?287ffff 1430000?143ffff sa324 1 0 1 0 0 0 1 0 0 128/64 2880000?289ffff 1440000?144ffff sa325 1 0 1 0 0 0 1 0 1 128/64 28a0000?28bffff 1450000?145ffff sa326 1 0 1 0 0 0 1 1 0 128/64 28c0000?28dffff 1460000?146ffff sa327 1 0 1 0 0 0 1 1 1 128/64 28e0000?28fffff 1470000?147ffff sa328 1 0 1 0 0 1 0 0 0 128/64 2900000?291ffff 1480000?148ffff sa329 1 0 1 0 0 1 0 0 1 128/64 2920000?293ffff 1490000?149ffff sa330 1 0 1 0 0 1 0 1 0 128/64 2940000?295ffff 14a0000?14affff sa331 1 0 1 0 0 1 0 1 1 128/64 2960000?297ffff 14b0000?14bffff sa332 1 0 1 0 0 1 1 0 0 128/64 2980000?299ffff 14c0000?14cffff sa333 1 0 1 0 0 1 1 0 1 128/64 29a0000?29bffff 14d0000?14dffff sa334 1 0 1 0 0 1 1 1 0 128/64 29c0000?29dffff 14e0000?14effff sa335 1 0 1 0 0 1 1 1 1 128/64 29e0000?29fffff 14f0000?14fffff sa336 1 0 1 0 1 0 0 0 0 128/64 2a00000?2a1ffff 1500000?150ffff sa337 1 0 1 0 1 0 0 0 1 128/64 2a20000?2a3ffff 1510000?151ffff sa338 1 0 1 0 1 0 0 1 0 128/64 2a40000?2a5ffff 1520000?152ffff sa339 1 0 1 0 1 0 0 1 1 128/64 2a60000?2a7ffff 1530000?153ffff sa340 1 0 1 0 1 0 1 0 0 128/64 2a80000?2a9ffff 1540000?154ffff sa341 1 0 1 0 1 0 1 0 1 128/64 2aa0000?2abffff 1550000?155ffff sa342 1 0 1 0 1 0 1 1 0 128/64 2ac0000?2adffff 1560000?156ffff sa343 1 0 1 0 1 0 1 1 1 128/64 2ae00000?2efffff 1570000?157ffff sa344 1 0 1 0 1 1 0 0 0 128/64 2b00000?2b1ffff 1580000?158ffff sa345 1 0 1 0 1 1 0 0 1 128/64 2b20000?2b3ffff 1590000?159ffff sa346 1 0 1 0 1 1 0 1 0 128/64 2b40000?2b5ffff 15a0000?15affff sa347 1 0 1 0 1 1 0 1 1 128/64 2b60000?2b7ffff 15b0000?15bffff sa348 1 0 1 0 1 1 1 0 0 128/64 2b80000?2b9ffff 15c0000?15cffff sa349 1 0 1 0 1 1 1 0 1 128/64 2ba0000?2bbffff 15d0000?15dffff sa350 1 0 1 0 1 1 1 1 0 128/64 2bc0000?2dfffff 15e0000?15effff sa351 1 0 1 0 1 1 1 1 1 128/64 2be0000?2bfffff 15f0000?15fffff sa352 1 0 1 1 0 0 0 0 0 128/64 2c00000?2c1ffff 1600000?160ffff sa353 1 0 1 1 0 0 0 0 1 128/64 2c20000?2c3ffff 1610000?161ffff sa354 1 0 1 1 0 0 0 1 0 128/64 2c40000?2c5ffff 1620000?162ffff sa355 1 0 1 1 0 0 0 1 1 128/64 2c60000?2c7ffff 1630000?163ffff sa356 1 0 1 1 0 0 1 0 0 128/64 2c80000?2c9ffff 1640000?164ffff sector address table?s29gl512n (sheet 8 of 12) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 21 of 92 s29gl512n S29GL256N s29gl128n sa357 1 0 1 1 0 0 1 0 1 128/64 2ca0000?2cbffff 1650000?165ffff sa358 1 0 1 1 0 0 1 1 0 128/64 2cc0000?2cdffff 1660000?166ffff sa359 1 0 1 1 0 0 1 1 1 128/64 2ce0000?2cfffff 1670000?167ffff sa360 1 0 1 1 0 1 0 0 0 128/64 2d00000?2d1ffff 1680000?168ffff sa361 1 0 1 1 0 1 0 0 1 128/64 2d20000?2d3ffff 1690000?169ffff sa362 1 0 1 1 0 1 0 1 0 128/64 2d40000?2d5ffff 16a0000?16affff sa363 1 0 1 1 0 1 0 1 1 128/64 2d60000?2d7ffff 16b0000?16bffff sa364 1 0 1 1 0 1 1 0 0 128/64 2d80000?2d9ffff 16c0000?16cffff sa365 1 0 1 1 0 1 1 0 1 128/64 2da0000?2dbffff 16d0000?16dffff sa366 1 0 1 1 0 1 1 1 0 128/64 2dc0000?2ddffff 16e0000?16effff sa367 1 0 1 1 0 1 1 1 1 128/64 2de0000?2dfffff 16f0000?16fffff sa368 1 0 1 1 1 0 0 0 0 128/64 2e00000?2e1ffff 1700000?170ffff sa369 1 0 1 1 1 0 0 0 1 128/64 2e20000?2e3ffff 1710000?171ffff sa370 1 0 1 1 1 0 0 1 0 128/64 2e40000?2e5ffff 1720000?172ffff sa371 1 0 1 1 1 0 0 1 1 128/64 2e60000?2e7ffff 1730000?173ffff sa372 1 0 1 1 1 0 1 0 0 128/64 2e80000?2e9ffff 1740000?174ffff sa373 1 0 1 1 1 0 1 0 1 128/64 2ea0000?2ebffff 1750000?175ffff sa374 1 0 1 1 1 0 1 1 0 128/64 2ec0000?2edffff 1760000?176ffff sa375 1 0 1 1 1 0 1 1 1 128/64 2ee0000?2efffff 1770000?177ffff sa376 1 0 1 1 1 1 0 0 0 128/64 2f00000?2f1ffff 1780000?178ffff sa377 1 0 1 1 1 1 0 0 1 128/64 2f20000?2f3ffff 1790000?179ffff sa378 1 0 1 1 1 1 0 1 0 128/64 2f40000?2f5ffff 17a0000?17affff sa379 1 0 1 1 1 1 0 1 1 128/64 2f60000?2f7ffff 17b0000?17bffff sa380 1 0 1 1 1 1 1 0 0 128/64 2f80000?2f9ffff 17c0000?17cffff sa381 1 0 1 1 1 1 1 0 1 128/64 2fa0000?2fbffff 17d0000?17dffff sa382 1 0 1 1 1 1 1 1 0 128/64 2fc0000?2fdffff 17e0000?17effff sa383 1 0 1 1 1 1 1 1 1 128/64 3fe0000?3ffffff 17f0000?17fffff sa384 1 1 0 0 0 0 0 0 0 128/64 3000000?301ffff 1800000?180ffff sa385 1 1 0 0 0 0 0 0 1 128/64 3020000?303ffff 1810000?181ffff sa386 1 1 0 0 0 0 0 1 0 128/64 3040000?305ffff 1820000?182ffff sa387 1 1 0 0 0 0 0 1 1 128/64 3060000?307ffff 1830000?183ffff sa388 1 1 0 0 0 0 1 0 0 128/64 3080000?309ffff 1840000?184ffff sa389 1 1 0 0 0 0 1 0 1 128/64 30a0000?30bffff 1850000?185ffff sa390 1 1 0 0 0 0 1 1 0 128/64 30c0000?30dffff 1860000?186ffff sa391 1 1 0 0 0 0 1 1 1 128/64 30e0000?30fffff 1870000?187ffff sa392 1 1 0 0 0 1 0 0 0 128/64 3100000?311ffff 1880000?188ffff sa393 1 1 0 0 0 1 0 0 1 128/64 3120000?313ffff 1890000?189ffff sa394 1 1 0 0 0 1 0 1 0 128/64 3140000?315ffff 18a0000?18affff sa395 1 1 0 0 0 1 0 1 1 128/64 3160000?317ffff 18b0000?18bffff sa396 1 1 0 0 0 1 1 0 0 128/64 3180000?319ffff 18c0000?18cffff sa397 1 1 0 0 0 1 1 0 1 128/64 31a0000?31bffff 18d0000?18dffff sa398 1 1 0 0 0 1 1 1 0 128/64 31c0000?31dffff 18e0000?18effff sa399 1 1 0 0 0 1 1 1 1 128/64 31e0000?31fffff 18f0000?18fffff sa400 1 1 0 0 1 0 0 0 0 128/64 3200000?321ffff 1900000?190ffff sa401 1 1 0 0 1 0 0 0 1 128/64 3220000?323ffff 1910000?191ffff sector address table?s29gl512n (sheet 9 of 12) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 22 of 92 s29gl512n S29GL256N s29gl128n sa402 1 1 0 0 1 0 0 1 0 128/64 3240000?325ffff 1920000?192ffff sa403 1 1 0 0 1 0 0 1 1 128/64 3260000?327ffff 1930000?193ffff sa404 1 1 0 0 1 0 1 0 0 128/64 3280000?329ffff 1940000?194ffff sa405 1 1 0 0 1 0 1 0 1 128/64 32a0000?32bffff 1950000?195ffff sa406 1 1 0 0 1 0 1 1 0 128/64 32c0000?32dffff 1960000?196ffff sa407 1 1 0 0 1 0 1 1 1 128/64 32e0000?32fffff 1970000?197ffff sa408 1 1 0 0 1 1 0 0 0 128/64 3300000?331ffff 1980000?198ffff sa409 1 1 0 0 1 1 0 0 1 128/64 3320000?333ffff 1990000?199ffff sa410 1 1 0 0 1 1 0 1 0 128/64 3340000?335ffff 19a0000?19affff sa411 1 1 0 0 1 1 0 1 1 128/64 3360000?337ffff 19b0000?19bffff sa412 1 1 0 0 1 1 1 0 0 128/64 3380000?339ffff 19c0000?19cffff sa413 1 1 0 0 1 1 1 0 1 128/64 33a0000?33bffff 19d0000?19dffff sa414 1 1 0 0 1 1 1 1 0 128/64 33c0000?33dffff 19e0000?19effff sa415 1 1 0 0 1 1 1 1 1 128/64 33e0000?33fffff 19f0000?19fffff sa416 1 1 0 1 0 0 0 0 0 128/64 3400000?341ffff 1a00000?1a0ffff sa417 1 1 0 1 0 0 0 0 1 128/64 3420000?343ffff 1a10000?1a1ffff sa418 1 1 0 1 0 0 0 1 0 128/64 3440000?345ffff 1a20000?1a2ffff sa419 1 1 0 1 0 0 0 1 1 128/64 3460000?347ffff 1a30000?1a3ffff sa420 1 1 0 1 0 0 1 0 0 128/64 3480000?349ffff 1a40000?1a4ffff sa421 1 1 0 1 0 0 1 0 1 128/64 34a0000?34bffff 1a50000?1a5ffff sa422 1 1 0 1 0 0 1 1 0 128/64 34c0000?34dffff 1a60000?1a6ffff sa423 1 1 0 1 0 0 1 1 1 128/64 34e0000?34fffff 1a70000?1a7ffff sa424 1 1 0 1 0 1 0 0 0 128/64 3500000?351ffff 1a80000?1a8ffff sa425 1 1 0 1 0 1 0 0 1 128/64 3520000?353ffff 1a90000?1a9ffff sa426 1 1 0 1 0 1 0 1 0 128/64 3540000?355ffff 1aa0000?1aaffff sa427 1 1 0 1 0 1 0 1 1 128/64 3560000?357ffff 1ab0000?1abffff sa428 1 1 0 1 0 1 1 0 0 128/64 3580000?359ffff 1ac0000?1acffff sa429 1 1 0 1 0 1 1 0 1 128/64 35a0000?35bffff 1ad0000?1adffff sa430 1 1 0 1 0 1 1 1 0 128/64 35c0000?35dffff 1ae0000?1aeffff sa431 1 1 0 1 0 1 1 1 1 128/64 35e0000?35fffff 1af0000?1afffff sa432 1 1 0 1 1 0 0 0 0 128/64 3600000?361ffff 1b00000?1b0ffff sa433 1 1 0 1 1 0 0 0 1 128/64 3620000?363ffff 1b10000?1b1ffff sa434 1 1 0 1 1 0 0 1 0 128/64 3640000?365ffff 1b20000?1b2ffff sa435 1 1 0 1 1 0 0 1 1 128/64 3660000?367ffff 1b30000?1b3ffff sa436 1 1 0 1 1 0 1 0 0 128/64 3680000?369ffff 1b40000?1b4ffff sa437 1 1 0 1 1 0 1 0 1 128/64 36a0000?36bffff 1b50000?1b5ffff sa438 1 1 0 1 1 0 1 1 0 128/64 36c0000?36dffff 1b60000?1b6ffff sa439 1 1 0 1 1 0 1 1 1 128/64 36e0000?36fffff 1b70000?1b7ffff sa440 1 1 0 1 1 1 0 0 0 128/64 3700000?371ffff 1b80000?1b8ffff sa441 1 1 0 1 1 1 0 0 1 128/64 3720000?373ffff 1b90000?1b9ffff sa442 1 1 0 1 1 1 0 1 0 128/64 3740000?375ffff 1ba0000?1baffff sa443 1 1 0 1 1 1 0 1 1 128/64 3760000?377ffff 1bb0000?1bbffff sa444 1 1 0 1 1 1 1 0 0 128/64 3780000?379ffff 1bc0000?1bcffff sa445 1 1 0 1 1 1 1 0 1 128/64 37a0000?37bffff 1bd0000?1bdffff sa446 1 1 0 1 1 1 1 1 0 128/64 37c0000?37dffff 1be0000?1beffff sector address table?s29gl512n (sheet 10 of 12) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 23 of 92 s29gl512n S29GL256N s29gl128n sa447 1 1 0 1 1 1 1 1 1 128/64 37e0000?37fffff 1bf0000?1bfffff sa448 1 1 1 0 0 0 0 0 0 128/64 3800000?381ffff 1c00000?1c0ffff sa449 1 1 1 0 0 0 0 0 1 128/64 3820000?383ffff 1c10000?1c1ffff sa450 1 1 1 0 0 0 0 1 0 128/64 3840000?385ffff 1c20000?1c2ffff sa451 1 1 1 0 0 0 0 1 1 128/64 3860000?387ffff 1c30000?1c3ffff sa452 1 1 1 0 0 0 1 0 0 128/64 3880000?389ffff 1c40000?1c4ffff sa453 1 1 1 0 0 0 1 0 1 128/64 38a0000?38bffff 1c50000?1c5ffff sa454 1 1 1 0 0 0 1 1 0 128/64 38c0000?38dffff 1c60000?1c6ffff sa455 1 1 1 0 0 0 1 1 1 128/64 38e0000?38fffff 1c70000?1c7ffff sa456 1 1 1 0 0 1 0 0 0 128/64 3900000?391ffff 1c80000?1c8ffff sa457 1 1 1 0 0 1 0 0 1 128/64 3920000?393ffff 1c90000?1c9ffff sa458 1 1 1 0 0 1 0 1 0 128/64 3940000?395ffff 1ca0000?1caffff sa459 1 1 1 0 0 1 0 1 1 128/64 3960000?397ffff 1cb0000?1cbffff sa460 1 1 1 0 0 1 1 0 0 128/64 3980000?399ffff 1cc0000?1ccffff sa461 1 1 1 0 0 1 1 0 1 128/64 39a0000?39bffff 1cd0000?1cdffff sa462 1 1 1 0 0 1 1 1 0 128/64 39c0000?39dffff 1ce0000?1ceffff sa463 1 1 1 0 0 1 1 1 1 128/64 39e0000?39fffff 1cf0000?1cfffff sa464 1 1 1 0 1 0 0 0 0 128/64 3a00000?3a1ffff 1d00000?1d0ffff sa465 1 1 1 0 1 0 0 0 1 128/64 3a20000?3a3ffff 1d10000?1d1ffff sa466 1 1 1 0 1 0 0 1 0 128/64 3a40000?3a5ffff 1d20000?1d2ffff sa467 1 1 1 0 1 0 0 1 1 128/64 3a60000?3a7ffff 1d30000?1d3ffff sa468 1 1 1 0 1 0 1 0 0 128/64 3a80000?3a9ffff 1d40000?1d4ffff sa469 1 1 1 0 1 0 1 0 1 128/64 3aa0000?3abffff 1d50000?1d5ffff sa470 1 1 1 0 1 0 1 1 0 128/64 3ac0000?3adffff 1d60000?1d6ffff sa471 1 1 1 0 1 0 1 1 1 128/64 3ae0000?3afffff 1d70000?1d7ffff sa472 1 1 1 0 1 1 0 0 0 128/64 3b00000?3b1ffff 1d80000?1d8ffff sa473 1 1 1 0 1 1 0 0 1 128/64 3b20000?3b3ffff 1d90000?1d9ffff sa474 1 1 1 0 1 1 0 1 0 128/64 3b40000?3b5ffff 1da0000?1daffff sa475 1 1 1 0 1 1 0 1 1 128/64 3b60000?3b7ffff 1db0000?1dbffff sa476 1 1 1 0 1 1 1 0 0 128/64 3b80000?3b9ffff 1dc0000?1dcffff sa477 1 1 1 0 1 1 1 0 1 128/64 3ba0000?3bbffff 1dd0000?1ddffff sa478 1 1 1 0 1 1 1 1 0 128/64 3bc0000?3bdffff 1de0000?1deffff sa479 1 1 1 0 1 1 1 1 1 128/64 3be0000?3bfffff 1df0000?1dfffff sa480 1 1 1 1 0 0 0 0 0 128/64 3c00000?3c1ffff 1e00000?1e0ffff sa481 1 1 1 1 0 0 0 0 1 128/64 3c20000?3c3ffff 1e10000?1e1ffff sa482 1 1 1 1 0 0 0 1 0 128/64 3c40000?3c5ffff 1e20000?1e2ffff sa483 1 1 1 1 0 0 0 1 1 128/64 3c60000?3c7ffff 1e30000?1e3ffff sa484 1 1 1 1 0 0 1 0 0 128/64 3c80000?3c9ffff 1e40000?1e4ffff sa485 1 1 1 1 0 0 1 0 1 128/64 3ca0000?3cbffff 1e50000?1e5ffff sa486 1 1 1 1 0 0 1 1 0 128/64 3cc0000?3cdffff 1e60000?1e6ffff sa487 1 1 1 1 0 0 1 1 1 128/64 3ce0000?3cfffff 1e70000?1e7ffff sa488 1 1 1 1 0 1 0 0 0 128/64 3d00000?3d1fffff 1e80000?1e8ffff sa489 1 1 1 1 0 1 0 0 1 128/64 3d20000?3d3ffff 1e90000?1e9ffff sa490 1 1 1 1 0 1 0 1 0 128/64 3d40000?3d5ffff 1ea0000?1eaffff sa491 1 1 1 1 0 1 0 1 1 128/64 3d60000?3d7ffff 1eb0000?1ebffff sector address table?s29gl512n (sheet 11 of 12) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 24 of 92 s29gl512n S29GL256N s29gl128n sa492 1 1 1 1 0 1 1 0 0 128/64 3d80000?3d9ffff 1ec0000?1ecffff sa493 1 1 1 1 0 1 1 0 1 128/64 3da0000?3dbffff 1ed0000?1edffff sa494 1 1 1 1 0 1 1 1 0 128/64 3dc0000?3ddffff 1ee0000?1eeffff sa495 1 1 1 1 0 1 1 1 1 128/64 3de0000?3dfffff 1ef0000?1efffff sa496 1 1 1 1 1 0 0 0 0 128/64 3e00000?3e1ffff 1f00000?1f0ffff sa497 1 1 1 1 1 0 0 0 1 128/64 3e20000?3e3ffff 1f10000?1f1ffff sa498 1 1 1 1 1 0 0 1 0 128/64 3e40000?3e5ffff 1f20000?1f2ffff sa499 1 1 1 1 1 0 0 1 1 128/64 3e60000?3e7ffff 1f30000?1f3ffff sa500 1 1 1 1 1 0 1 0 0 128/64 3e80000?3e9ffff 1f40000?1f4ffff sa501 1 1 1 1 1 0 1 0 1 128/64 3ea0000?3ebffff 1f50000?1f5ffff sa502 1 1 1 1 1 0 1 1 0 128/64 3ec00000?3edffff 1f60000?1f6ffff sa503 1 1 1 1 1 0 1 1 1 128/64 3ee0000?3efffff 1f70000?1f7ffff sa504 1 1 1 1 1 1 0 0 0 128/64 3f00000?3f1ffff 1f80000?1f8ffff sa505 1 1 1 1 1 1 0 0 1 128/64 3f20000?3f3ffff 1f90000?1f9ffff sa506 1 1 1 1 1 1 0 1 0 128/64 3f40000?3f5ffff 1fa0000?1faffff sa507 1 1 1 1 1 1 0 1 1 128/64 3f60000?3f7ffff 1fb0000?1fbffff sa508 1 1 1 1 1 1 1 0 0 128/64 3f80000?3f9ffff 1fc0000?1fcffff sa509 1 1 1 1 1 1 1 0 1 128/64 3fa0000?3fbffff 1fd0000?1fdffff sa510 1 1 1 1 1 1 1 1 0 128/64 3fc0000?3fdffff 1fe0000?1feffff sa511 1 1 1 1 1 1 1 1 1 128/64 3fe0000?3ffffff 1ff0000?1ffffff sector address table?s29gl512n (sheet 12 of 12) sector a24?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 25 of 92 s29gl512n S29GL256N s29gl128n sector address table?S29GL256N (sheet 1 of 6) sector a23?a16 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 00000000 128/64 0000000?001ffff 0000000?000ffff sa1 00000001 128/64 0020000?003ffff 0010000?001ffff sa2 00000010 128/64 0040000?005ffff 0020000?002ffff sa3 00000011 128/64 0060000?007ffff 0030000?003ffff sa4 00000100 128/64 0080000?009ffff 0040000?004ffff sa5 00000101 128/64 00a0000?00bffff 0050000?005ffff sa6 00000110 128/64 00c0000?00dffff 0060000?006ffff sa7 00000111 128/64 00e0000?00fffff 0070000?007ffff sa8 00001000 128/64 0100000?011ffff 0080000?008ffff sa9 00001001 128/64 0120000?013ffff 0090000?009ffff sa10 00001010 128/64 0140000?015ffff 00a0000?00affff sa11 00001011 128/64 0160000?017ffff 00b0000?00bffff sa12 00001100 128/64 0180000?019ffff 00c0000?00cffff sa13 00001101 128/64 01a0000?01bffff 00d0000?00dffff sa14 00001110 128/64 01c0000?01dffff 00e0000?00effff sa15 00001111 128/64 01e0000?01fffff 00f0000?00fffff sa16 00010000 128/64 0200000?021ffff 0100000?010ffff sa17 00010001 128/64 0220000?023ffff 0110000?011ffff sa18 00010010 128/64 0240000?025ffff 0120000?012ffff sa19 00010011 128/64 0260000?027ffff 0130000?013ffff sa20 00010100 128/64 0280000?029ffff 0140000?014ffff sa21 00010101 128/64 02a0000?02bffff 0150000?015ffff sa22 00010110 128/64 02c0000?02dffff 0160000?016ffff sa23 00010111 128/64 02e0000?02fffff 0170000?017ffff sa24 00011000 128/64 0300000?031ffff 0180000?018ffff sa25 00011001 128/64 0320000?033ffff 0190000?019ffff sa26 00011010 128/64 0340000?035ffff 01a0000?01affff sa27 00011011 128/64 0360000?037ffff 01b0000?01bffff sa28 00011100 128/64 0380000?039ffff 01c0000?01cffff sa29 00011101 128/64 03a0000?03bffff 01d0000?01dffff sa30 00011110 128/64 03c0000?03dffff 01e0000?01effff sa31 00011111 128/64 03e0000?03fffff 01f0000?01fffff sa32 00100000 128/64 0400000?041ffff 0200000?020ffff sa33 00100001 128/64 0420000?043ffff 0210000?021ffff sa34 00100010 128/64 0440000?045ffff 0220000?022ffff sa35 00100011 128/64 0460000?047ffff 0230000?023ffff sa36 00100100 128/64 0480000?049ffff 0240000?024ffff sa37 00100101 128/64 04a0000?04bffff 0250000?025ffff sa38 00100110 128/64 04c0000?04dffff 0260000?026ffff sa39 00100111 128/64 04e0000?04fffff 0270000?027ffff sa40 00101000 128/64 0500000?051ffff 0280000?028ffff sa41 00101001 128/64 0520000?053ffff 0290000?029ffff sa42 00101010 128/64 0540000?055ffff 02a0000?02affff sa43 00101011 128/64 0560000?057ffff 02b0000?02bffff not recommended for new design
document number: 002-01522 rev. *b page 26 of 92 s29gl512n S29GL256N s29gl128n sa44 00101100 128/64 0580000?059ffff 02c0000?02cffff sa45 00101101 128/64 05a0000?05bffff 02d0000?02dffff sa46 00101110 128/64 05c0000?05dffff 02e0000?02effff sa47 00101111 128/64 05e0000?05fffff 02f0000?02fffff sa48 00110000 128/64 0600000?061ffff 0300000?030ffff sa49 00110001 128/64 0620000?063ffff 0310000?031ffff sa50 00110010 128/64 0640000?065ffff 0320000?032ffff sa51 00110011 128/64 0660000?067ffff 0330000?033ffff sa52 00110100 128/64 0680000?069ffff 0340000?034ffff sa53 00110101 128/64 06a0000?06bffff 0350000?035ffff sa54 00110110 128/64 06c0000?06dffff 0360000?036ffff sa55 00110111 128/64 06e0000?06fffff 0370000?037ffff sa56 00111000 128/64 0700000?071ffff 0380000?038ffff sa57 00111001 128/64 0720000?073ffff 0390000?039ffff sa58 00111010 128/64 0740000?075ffff 03a0000?03affff sa59 00111011 128/64 0760000?077ffff 03b0000?03bffff sa60 00111100 128/64 0780000?079ffff 03c0000?03cffff sa61 00111101 128/64 07a0000?7bffff 03d0000?03dffff sa62 00111110 128/64 07c0000?07dffff 03e0000?03effff sa63 00111111 128/64 07e0000?07fffff0 03f0000?03fffff sa64 01000000 128/64 0800000?081ffff 0400000?040ffff sa65 01000001 128/64 0820000?083ffff 0410000?041ffff sa66 01000010 128/64 0840000?085ffff 0420000?042ffff sa67 01000011 128/64 0860000?087ffff 0430000?043ffff sa68 01000100 128/64 0880000?089ffff 0440000?044ffff sa69 01000101 128/64 08a0000?08bffff 0450000?045ffff sa70 01000110 128/64 08c0000?08dffff 0460000?046ffff sa71 01000111 128/64 08e0000?08fffff 0470000?047ffff sa72 01001000 128/64 0900000?091ffff 0480000?048ffff sa73 01001001 128/64 0920000?093ffff 0490000?049ffff sa74 01001010 128/64 0940000?095ffff 04a0000?04affff sa75 01001011 128/64 0960000?097ffff 04b0000?04bffff sa76 01001100 128/64 0980000?099ffff 04c0000?04cffff sa77 01001101 128/64 09a0000?09bffff 04d0000?04dffff sa78 01001110 128/64 09c0000?09dffff 04e0000?04effff sa79 01001111 128/64 09e0000?09fffff 04f0000?04fffff sa80 01010000 128/64 0a00000?0a1ffff 0500000?050ffff sa81 01010001 128/64 0a20000?0a3ffff 0510000?051ffff sa82 01010010 128/64 0a40000?045ffff 0520000?052ffff sa83 01010011 128/64 0a60000?0a7ffff 0530000?053ffff sa84 01010100 128/64 0a80000?0a9ffff 0540000?054ffff sa85 01010101 128/64 0aa0000?0abffff 0550000?055ffff sa86 01010110 128/64 0ac0000?0adffff 0560000?056ffff sa87 01010111 128/64 0ae0000?aefffff 0570000?057ffff sa88 01011000 128/64 0b00000?0b1ffff 0580000?058ffff sector address table?S29GL256N (sheet 2 of 6) sector a23?a16 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 27 of 92 s29gl512n S29GL256N s29gl128n sa89 01011001 128/64 0b20000?0b3ffff 0590000?059ffff sa90 01011010 128/64 0b40000?0b5ffff 05a0000?05affff sa91 01011011 128/64 0b60000?0b7ffff 05b0000?05bffff sa92 01011100 128/64 0b80000?0b9ffff 05c0000?05cffff sa93 01011101 128/64 0ba0000?0bbffff 05d0000?05dffff sa94 01011110 128/64 0bc0000?0bdffff 05e0000?05effff sa95 01011111 128/64 0be0000?0bfffff 05f0000?05fffff sa96 01100000 128/64 0c00000?0c1ffff 0600000?060ffff sa97 01100001 128/64 0c20000?0c3ffff 0610000?061ffff sa98 01100010 128/64 0c40000?0c5ffff 0620000?062ffff sa99 01100011 128/64 0c60000?0c7ffff 0630000?063ffff sa100 01100100 128/64 0c80000?0c9ffff 0640000?064ffff sa101 01100101 128/64 0ca0000?0cbffff 0650000?065ffff sa102 01100110 128/64 0cc0000?0cdffff 0660000?066ffff sa103 01100111 128/64 0ce0000?0cfffff 0670000?067ffff sa104 01101000 128/64 0d00000?0d1ffff 0680000?068ffff sa105 01101001 128/64 0d20000?0d3ffff 0690000?069ffff sa106 01101010 128/64 0d40000?0d5ffff 06a0000?06affff sa107 01101011 128/64 0d60000?0d7ffff 06b0000?06bffff sa108 01101100 128/64 0d80000?0d9ffff 06c0000?06cffff sa109 01101101 128/64 0da0000?0dbffff 06d0000?06dffff sa110 01101110 128/64 0dc0000?0ddffff 06e0000?06effff sa111 01101111 128/64 0de0000?0dfffff 06f0000?06fffff sa112 01110000 128/64 0e00000?0e1ffff 0700000?070ffff sa113 01110001 128/64 0e20000?0e3ffff 0710000?071ffff sa114 01110010 128/64 0e40000?0e5ffff 0720000?072ffff sa115 01110011 128/64 0e60000?0e7ffff 0730000?073ffff sa116 01110100 128/64 0e80000?0e9ffff 0740000?074ffff sa117 01110101 128/64 0ea0000?0ebffff 0750000?075ffff sa118 01110110 128/64 0ec0000?0edffff 0760000?076ffff sa119 01110111 128/64 0ee0000?0efffff 0770000?077ffff sa120 01111000 128/64 0f00000?0f1ffff 0780000?078ffff sa121 01111001 128/64 0f20000?0f3ffff 0790000?079ffff sa122 01111010 128/64 0f40000?0f5ffff 07a0000?07affff sa123 01111011 128/64 0f60000?0f7ffff 07b0000?07bffff sa124 01111100 128/64 0f80000?0f9ffff 07c0000?07cffff sa125 01111101 128/64 0fa0000?0fbffff 07d0000?07dffff sa126 01111110 128/64 0fc0000?0fdffff 07e0000?07effff sa127 01111111 128/64 0fe0000?0ffffff 07f0000?07fffff sa128 10000000 128/64 1000000?101ffff 0800000?080ffff sa129 10000001 128/64 1020000?103ffff 0810000?081ffff sa130 10000010 128/64 1040000?105ffff 0820000?082ffff sa131 10000011 128/64 1060000?107ffff 0830000?083ffff sa132 10000100 128/64 1080000?109ffff 0840000?084ffff sa133 10000101 128/64 10a0000?10bffff 0850000?085ffff sector address table?S29GL256N (sheet 3 of 6) sector a23?a16 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 28 of 92 s29gl512n S29GL256N s29gl128n sa134 10000110 128/64 10c0000?10dffff 0860000?086ffff sa135 10000111 128/64 10e0000?10fffff 0870000?087ffff sa136 10001000 128/64 1100000?111ffff 0880000?088ffff sa137 10001001 128/64 1120000?113ffff 0890000?089ffff sa138 10001010 128/64 1140000?115ffff 08a0000?08affff sa139 10001011 128/64 1160000?117ffff 08b0000?08bffff sa140 10001100 128/64 1180000?119ffff 08c0000?08cffff sa141 10001101 128/64 11a0000?11bffff 08d0000?08dffff sa142 10001110 128/64 11c0000?11dffff 08e0000?08effff sa143 10001111 128/64 11e0000?11fffff 08f0000?08fffff sa144 10010000 128/64 1200000?121ffff 0900000?090ffff sa145 10010001 128/64 1220000?123ffff 0910000?091ffff sa146 10010010 128/64 1240000?125ffff 0920000?092ffff sa147 10010011 128/64 1260000?127ffff 0930000?093ffff sa148 10010100 128/64 1280000?129ffff 0940000?094ffff sa149 10010101 128/64 12a0000?12bffff 0950000?095ffff sa150 10010110 128/64 12c0000?12dffff 0960000?096ffff sa151 10010111 128/64 12e0000?12fffff 0970000?097ffff sa152 10011000 128/64 1300000?131ffff 0980000?098ffff sa153 10011001 128/64 1320000?133ffff 0990000?099ffff sa154 10011010 128/64 1340000?135ffff 09a0000?09affff sa155 10011011 128/64 1360000?137ffff 09b0000?09bffff sa156 10011100 128/64 1380000?139ffff 09c0000?09cffff sa157 10011101 128/64 13a0000?13bffff 09d0000?09dffff sa158 10011110 128/64 13c0000?13dffff 09e0000?09effff sa159 10011111 128/64 13e0000?13fffff 09f0000?09fffff sa160 10100000 128/64 1400000?141ffff 0a00000?0a0ffff sa161 10100001 128/64 1420000?143ffff 0a10000?0a1ffff sa162 10100010 128/64 1440000?145ffff 0a20000?0a2ffff sa163 10100011 128/64 1460000?147ffff 0a30000?0a3ffff sa164 10100100 128/64 1480000?149ffff 0a40000?0a4ffff sa165 10100101 128/64 14a0000?14bffff 0a50000?0a5ffff sa166 10100110 128/64 14c0000?14dffff 0a60000?0a6ffff sa167 10100111 128/64 14e0000?14fffff 0a70000?0a7ffff sa168 10101000 128/64 1500000?151ffff 0a80000?0a8ffff sa169 10101001 128/64 1520000?153ffff 0a90000?0a9ffff sa170 10101010 128/64 1540000?155ffff 0aa0000?0aaffff sa171 10101011 128/64 1560000?157ffff 0ab0000?0abffff sa172 10101100 128/64 1580000?159ffff 0ac0000?0acffff sa173 10101101 128/64 15a0000?15bffff 0ad0000?0adffff sa174 10101110 128/64 15c0000?15dffff 0ae0000?0aeffff sa175 10101111 128/64 15e0000?15fffff 0af0000?0afffff sa176 10110000 128/64 1600000?161ffff 0b00000?0b0ffff sa177 10110001 128/64 1620000?163ffff 0b10000?0b1ffff sa178 10110010 128/64 1640000?165fffff 0b20000?0b2ffff sector address table?S29GL256N (sheet 4 of 6) sector a23?a16 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 29 of 92 s29gl512n S29GL256N s29gl128n sa179 10110011 128/64 1660000?167ffff 0b30000?0b3ffff sa180 10110100 128/64 1680000?169ffff 0b40000?0b4ffff sa181 10110101 128/64 16a0000?16bffff 0b50000?0b5ffff sa182 10110110 128/64 16c0000?16dffff 0b60000?0b6ffff sa183 10110111 128/64 16e0000?16fffff 0b70000?0b7ffff sa184 10111000 128/64 1700000?171ffff 0b80000?0b8ffff sa185 10111001 128/64 1720000?173ffff 0b90000?0b9ffff sa186 10111010 128/64 1740000?175ffff 0ba0000?0baffff sa187 10111011 128/64 1760000?177ffff 0bb0000?0bbffff sa188 10111100 128/64 1780000?179ffff 0bc0000?0bcffff sa189 10111101 128/64 17a0000?17bffff 0bd0000?0bdffff sa190 10111110 128/64 17c0000?17dffff 0be0000?0beffff sa191 10111111 128/64 17e0000?17fffff 0bf0000?0bfffff sa192 11000000 128/64 1800000?181ffff 0c00000?0c0ffff sa193 11000001 128/64 1820000?183ffff 0c10000?0c1ffff sa194 11000010 128/64 1840000?185ffff 0c20000?0c2ffff sa195 11000011 128/64 1860000?187ffff 0c30000?0c3ffff sa196 11000100 128/64 1880000?189ffff 0c40000?0c4ffff sa197 11000101 128/64 18a0000?18bffff 0c50000?0c5ffff sa198 11000110 128/64 18c0000?18dffff 0c60000?0c6ffff sa199 11000111 128/64 18e0000?18fffff 0c70000?0c7ffff sa200 11001000 128/64 1900000?191ffff 0c80000?0c8ffff sa201 11001001 128/64 1920000?193ffff 0c90000?0c9ffff sa202 11001010 128/64 1940000?195ffff 0ca0000?0caffff sa203 11001011 128/64 1960000?197ffff 0cb0000?0cbffff sa204 11001100 128/64 1980000?199ffff 0cc0000?0ccffff sa205 11001101 128/64 19a0000?19bffff 0cd0000?0cdffff sa206 11001110 128/64 19c0000?19dffff 0ce0000?0ceffff sa207 11001111 128/64 19e0000?19ffff 0cf0000?0cfffff sa208 11010000 128/64 1a00000?1a1ffff 0d00000?0d0ffff sa209 11010001 128/64 1a20000?1a3ffff 0d10000?0d1ffff sa210 11010010 128/64 1a40000?1a5ffff 0d20000?0d2ffff sa211 11010011 128/64 1a60000?1a7ffff 0d30000?0d3ffff sa212 11010100 128/64 1a80000?1a9ffff 0d40000?0d4ffff sa213 11010101 128/64 1aa0000?1abffff 0d50000?0d5ffff sa214 11010110 128/64 1ac0000?1adffff 0d60000?0d6ffff sa215 11010111 128/64 1ae0000?1afffff 0d70000?0d7ffff sa216 11011000 128/64 1b00000?1b1ffff 0d80000?0d8ffff sa217 11011001 128/64 1b20000?1b3ffff 0d90000?0d9ffff sa218 11011010 128/64 1b40000?1b5ffff 0da0000?0daffff sa219 11011011 128/64 1b60000?1b7ffff 0db0000?0dbffff sa220 11011100 128/64 1b80000?1b9ffff 0dc0000?0dcffff sa221 11011101 128/64 1ba0000?1bbffff 0dd0000?0ddffff sa222 11011110 128/64 1bc0000?1bdffff 0de0000?0deffff sa223 11011111 128/64 1be0000?1bfffff 0df0000?0dfffff sector address table?S29GL256N (sheet 5 of 6) sector a23?a16 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 30 of 92 s29gl512n S29GL256N s29gl128n sa224 11100000 128/64 1c00000?1c1ffff 0e00000?0e0ffff sa225 11100001 128/64 1c20000?1c3ffff 0e10000?0e1ffff sa226 11100010 128/64 1c40000?1c5ffff 0e20000?0e2ffff sa227 11100011 128/64 1c60000?1c7ffff 0e30000?0e3ffff sa228 11100100 128/64 1c80000?1c9ffff 0e40000?0e4ffff sa229 11100101 128/64 1ca0000?1cbffff 0e50000?0e5ffff sa230 11100110 128/64 1cc0000?1cdffff 0e60000?0e6ffff sa231 11100111 128/64 1ce0000?1cfffff 0e70000?0e7ffff sa232 11101000 128/64 1d00000?1d1ffff 0e80000?0e8ffff sa233 11101001 128/64 1d20000?1d3ffff 0e90000?0e9ffff sa234 11101010 128/64 1d40000?1d5ffff 0ea0000?0eaffff sa235 11101011 128/64 1d60000?1d7ffff 0eb0000?0ebffff sa236 11101100 128/64 1d80000?1d9ffff 0ec0000?0ecffff sa237 11101101 128/64 1da0000?1dbffff 0ed0000?0edffff sa238 11101110 128/64 1dc0000?1ddffff 0ee0000?0eeffff sa239 11101111 128/64 1de0000?1dfffff 0ef0000?0efffff sa240 11110000 128/64 1e00000?1e1ffff 0f00000?0f0ffff sa241 11110001 128/64 1e20000?1e3ffff 0f10000?0f1ffff sa242 11110010 128/64 1e40000?1e5ffff 0f20000?0f2ffff sa243 11110011 128/64 1e60000?137ffff 0f30000?0f3ffff sa244 11110100 128/64 1e80000?1e9ffff 0f40000?0f4ffff sa245 11110101 128/64 1ea0000?1ebffff 0f50000?0f5ffff sa246 11110110 128/64 1ec0000?1edffff 0f60000?0f6ffff sa247 11110111 128/64 1ee0000?1efffff 0f70000?0f7ffff sa248 11111000 128/64 1f00000?1f1ffff 0f80000?0f8ffff sa249 11111001 128/64 1f20000?1f3ffff 0f90000?0f9ffff sa250 11111010 128/64 1f40000?1f5ffff 0fa0000?0faffff sa251 11111011 128/64 1f60000?1f7ffff 0fb0000?0fbffff sa252 11111100 128/64 1f80000?1f9ffff 0fc0000?0fcffff sa253 11111101 128/64 1fa0000?1fbffff 0fd0000?0fdffff sa254 11111110 128/64 1fc0000?1fdffff 0fe0000?0feffff sa255 11111111 128/64 1fe0000?1ffffff 0ff0000?0ffffff sector address table?S29GL256N (sheet 6 of 6) sector a23?a16 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 31 of 92 s29gl512n S29GL256N s29gl128n sector address table?s29gl128n (sheet 1 of 3) sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 0 0 0 0 0 0 0 128/64 0000000?001ffff 0000000?000ffff sa1 0 0 0 0 0 0 1 128/64 0020000?003ffff 0010000?001ffff sa2 0 0 0 0 0 1 0 128/64 0040000?005ffff 0020000?002ffff sa3 0 0 0 0 0 1 1 128/64 0060000?007ffff 0030000?003ffff sa4 0 0 0 0 1 0 0 128/64 0080000?009ffff 0040000?004ffff sa5 0 0 0 0 1 0 1 128/64 00a0000?00bffff 0050000?005ffff sa6 0 0 0 0 1 1 0 128/64 00c0000?00dffff 0060000?006ffff sa7 0 0 0 0 1 1 1 128/64 00e0000?00fffff 0070000?007ffff sa8 0 0 0 1 0 0 0 128/64 0100000?011ffff 0080000?008ffff sa9 0 0 0 1 0 0 1 128/64 0120000?013ffff 0090000?009ffff sa10 0 0 0 1 0 1 0 128/64 0140000?015ffff 00a0000?00affff sa11 0 0 0 1 0 1 1 128/64 0160000?017ffff 00b0000?00bffff sa12 0 0 0 1 1 0 0 128/64 0180000?019ffff 00c0000?00cffff sa13 0 0 0 1 1 0 1 128/64 01a0000?01bffff 00d0000?00dffff sa14 0 0 0 1 1 1 0 128/64 01c0000?01dffff 00e0000?00effff sa15 0 0 0 1 1 1 1 128/64 01e0000?01fffff 00f0000?00fffff sa16 0 0 1 0 0 0 0 128/64 0200000?021ffff 0100000?010ffff sa17 0 0 1 0 0 0 1 128/64 0220000?023ffff 0110000?011ffff sa18 0 0 1 0 0 1 0 128/64 0240000?025ffff 0120000?012ffff sa19 0 0 1 0 0 1 1 128/64 0260000?027ffff 0130000?013ffff sa20 0 0 1 0 1 0 0 128/64 0280000?029ffff 0140000?014ffff sa21 0 0 1 0 1 0 1 128/64 02a0000?02bffff 0150000?015ffff sa22 0 0 1 0 1 1 0 128/64 02c0000?02dffff 0160000?016ffff sa23 0 0 1 0 1 1 1 128/64 02e0000?02fffff 0170000?017ffff sa24 0 0 1 1 0 0 0 128/64 0300000?031ffff 0180000?018ffff sa25 0 0 1 1 0 0 1 128/64 0320000?033ffff 0190000?019ffff sa26 0 0 1 1 0 1 0 128/64 0340000?035ffff 01a0000?01affff sa27 0 0 1 1 0 1 1 128/64 0360000?037ffff 01b0000?01bffff sa28 0 0 1 1 1 0 0 128/64 0380000?039ffff 01c0000?01cffff sa29 0 0 1 1 1 0 1 128/64 03a0000?03bffff 01d0000?01dffff sa30 0 0 1 1 1 1 0 128/64 03c0000?03dffff 01e0000?01effff sa31 0 0 1 1 1 1 1 128/64 03e0000?03fffff 01f0000?01fffff sa32 0 1 0 0 0 0 0 128/64 0400000?041ffff 0200000?020ffff sa33 0 1 0 0 0 0 1 128/64 0420000?043ffff 0210000?021ffff sa34 0 1 0 0 0 1 0 128/64 0440000?045ffff 0220000?022ffff sa35 0 1 0 0 0 1 1 128/64 0460000?047ffff 0230000?023ffff sa36 0 1 0 0 1 0 0 128/64 0480000?049ffff 0240000?024ffff sa37 0 1 0 0 1 0 1 128/64 04a0000?04bffff 0250000?025ffff sa38 0 1 0 0 1 1 0 128/64 04c0000?04dffff 0260000?026ffff sa39 0 1 0 0 1 1 1 128/64 04e0000?04fffff 0270000?027ffff sa40 0 1 0 1 0 0 0 128/64 0500000?051ffff 0280000?028ffff sa41 0 1 0 1 0 0 1 128/64 0520000?053ffff 0290000?029ffff sa42 0 1 0 1 0 1 0 128/64 0540000?055ffff 02a0000?02affff sa43 0 1 0 1 0 1 1 128/64 0560000?057ffff 02b0000?02bffff not recommended for new design
document number: 002-01522 rev. *b page 32 of 92 s29gl512n S29GL256N s29gl128n sa44 0 1 0 1 1 0 0 128/64 0580000?059ffff 02c0000?02cffff sa45 0 1 0 1 1 0 1 128/64 05a0000?05bffff 02d0000?02dffff sa46 0 1 0 1 1 1 0 128/64 05c0000?05dffff 02e0000?02effff sa47 0 1 0 1 1 1 1 128/64 05e0000?05fffff 02f0000?02fffff sa48 0 1 1 0 0 0 0 128/64 0600000?061ffff 0300000?030ffff sa49 0 1 1 0 0 0 1 128/64 0620000?063ffff 0310000?031ffff sa50 0 1 1 0 0 1 0 128/64 0640000?065ffff 0320000?032ffff sa51 0 1 1 0 0 1 1 128/64 0660000?067ffff 0330000?033ffff sa52 0 1 1 0 1 0 0 128/64 0680000?069ffff 0340000?034ffff sa53 0 1 1 0 1 0 1 128/64 06a0000?06bffff 0350000?035ffff sa54 0 1 1 0 1 1 0 128/64 06c0000?06dffff 0360000?036ffff sa55 0 1 1 0 1 1 1 128/64 06e0000?06fffff 0370000?037ffff sa56 0 1 1 1 0 0 0 128/64 0700000?071ffff 0380000?038ffff sa57 0 1 1 1 0 0 1 128/64 0720000?073ffff 0390000?039ffff sa58 0 1 1 1 0 1 0 128/64 0740000?075ffff 03a0000?03affff sa59 0 1 1 1 0 1 1 128/64 0760000?077ffff 03b0000?03bffff sa60 0 1 1 1 1 0 0 128/64 0780000?079ffff 03c0000?03cffff sa61 0 1 1 1 1 0 1 128/64 07a0000?07bffff 03d0000?03dffff sa62 0 1 1 1 1 1 0 128/64 07c0000?07dffff 03e0000?03effff sa63 0 1 1 1 1 1 1 128/64 07e0000?07fffff 03f0000?03fffff sa64 1 0 0 0 0 0 0 128/64 0800000?081ffff 0400000?040ffff sa65 1 0 0 0 0 0 1 128/64 0820000?083ffff 0410000?041ffff sa66 1 0 0 0 0 1 0 128/64 0840000?085ffff 0420000?042ffff sa67 1 0 0 0 0 1 1 128/64 0860000?087ffff 0430000?043ffff sa68 1 0 0 0 1 0 0 128/64 0880000?089ffff 0440000?044ffff sa69 1 0 0 0 1 0 1 128/64 08a0000?08bffff 0450000?045ffff sa70 1 0 0 0 1 1 0 128/64 08c0000?08dffff 0460000?046ffff sa71 1 0 0 0 1 1 1 128/64 08e0000?08fffff 0470000?047ffff sa72 1 0 0 1 0 0 0 128/64 0900000?091ffff 0480000?048ffff sa73 1 0 0 1 0 0 1 128/64 0920000?093ffff 0490000?049ffff sa74 1 0 0 1 0 1 0 128/64 0940000?095ffff 04a0000?04affff sa75 1 0 0 1 0 1 1 128/64 0960000?097ffff 04b0000?04bffff sa76 1 0 0 1 1 0 0 128/64 0980000?099ffff 04c0000?04cffff sa77 1 0 0 1 1 0 1 128/64 09a0000?09bffff 04d0000?04dffff sa78 1 0 0 1 1 1 0 128/64 09c0000?09dffff 04e0000?04effff sa79 1 0 0 1 1 1 1 128/64 09e0000?09fffff 04f0000?04fffff sa80 1 0 1 0 0 0 0 128/64 0a00000?0a1ffff 0500000?050ffff sa81 1 0 1 0 0 0 1 128/64 0a20000?0a3ffff 0510000?051ffff sa82 1 0 1 0 0 1 0 128/64 0a40000?0a5ffff 0520000?052ffff sa83 1 0 1 0 0 1 1 128/64 0a60000?0a7ffff 0530000?053ffff sa84 1 0 1 0 1 0 0 128/64 0a80000?0a9ffff 0540000?054ffff sa85 1 0 1 0 1 0 1 128/64 0aa0000?0abffff 0550000?055ffff sa86 1 0 1 0 1 1 0 128/64 0ac0000?0adffff 0560000?056ffff sa87 1 0 1 0 1 1 1 128/64 0ae0000?0afffff 0570000?057ffff sector address table?s29gl128n (sheet 2 of 3) sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 33 of 92 s29gl512n S29GL256N s29gl128n sa88 1 0 1 1 0 0 0 128/64 0b00000?0b1ffff 0580000?058ffff sa89 1 0 1 1 0 0 1 128/64 0b20000?0b3ffff 0590000?059ffff sa90 1 0 1 1 0 1 0 128/64 0b40000?0b5ffff 05a0000?05affff sa91 1 0 1 1 0 1 1 128/64 0b60000?0b7ffff 05b0000?05bffff sa92 1 0 1 1 1 0 0 128/64 0b80000?0b9ffff 05c0000?05cffff sa93 1 0 1 1 1 0 1 128/64 0ba0000?0bbffff 05d0000?05dffff sa94 1 0 1 1 1 1 0 128/64 0bc0000?0bdffff 05e0000?05effff sa95 1 0 1 1 1 1 1 128/64 0be0000?0bfffff 05f0000?05fffff sa96 1 1 0 0 0 0 0 128/64 0c00000?0c1ffff 0600000?060ffff sa97 1 1 0 0 0 0 1 128/64 0c20000?0c3ffff 0610000?061ffff sa98 1 1 0 0 0 1 0 128/64 0c40000?0c5ffff 0620000?062ffff sa99 1 1 0 0 0 1 1 128/64 0c60000?0c7ffff 0630000?063ffff sa100 1 1 0 0 1 0 0 128/64 0c80000?0c9ffff 0640000?064ffff sa101 1 1 0 0 1 0 1 128/64 0ca0000?0cbffff 0650000?065ffff sa102 1 1 0 0 1 1 0 128/64 0cc0000?0cdffff 0660000?066ffff sa103 1 1 0 0 1 1 1 128/64 0ce0000?0cfffff 0670000?067ffff sa104 1 1 0 1 0 0 0 128/64 0d00000?0d1ffff 0680000?068ffff sa105 1 1 0 1 0 0 1 128/64 0d20000?0d3ffff 0690000?069ffff sa106 1 1 0 1 0 1 0 128/64 0d40000?0d5ffff 06a0000?06affff sa107 1 1 0 1 0 1 1 128/64 0d60000?0d7ffff 06b0000?06bffff sa108 1 1 0 1 1 0 0 128/64 0d80000?0d9ffff 06c0000?06cffff sa109 1 1 0 1 1 0 1 128/64 0da0000?0dbffff 06d0000?06dffff sa110 1 1 0 1 1 1 0 128/64 0dc0000?0ddffff 06e0000?06effff sa111 1 1 0 1 1 1 1 128/64 0de0000?0dfffff 06f0000?06fffff sa112 1 1 1 0 0 0 0 128/64 0e00000?0e1ffff 0700000?070ffff sa113 1 1 1 0 0 0 1 128/64 0e20000?0e3ffff 0710000?071ffff sa114 1 1 1 0 0 1 0 128/64 0e40000?0e5ffff 0720000?072ffff sa115 1 1 1 0 0 1 1 128/64 0e60000?0e7ffff 0730000?073ffff sa116 1 1 1 0 1 0 0 128/64 0e80000?0e9ffff 0740000?074ffff sa117 1 1 1 0 1 0 1 128/64 0ea0000?0ebffff 0750000?075ffff sa118 1 1 1 0 1 1 0 128/64 0ec0000?0edffff 0760000?076ffff sa119 1 1 1 0 1 1 1 128/64 0ee0000?0efffff 0770000?077ffff sa120 1 1 1 1 0 0 0 128/64 0f00000?0f1ffff 0780000?078ffff sa121 1 1 1 1 0 0 1 128/64 0f20000?0f3ffff 0790000?079ffff sa122 1 1 1 1 0 1 0 128/64 0f40000?0f5ffff 07a0000?07affff sa123 1 1 1 1 0 1 1 128/64 0f60000?0f7ffff 07b0000?07bffff sa124 1 1 1 1 1 0 0 128/64 0f80000?0f9ffff 07c0000?07cffff sa125 1 1 1 1 1 0 1 128/64 0fa0000?0fbffff 07d0000?07dffff sa126 1 1 1 1 1 1 0 128/64 0fc0000?0fdffff 07e0000?07effff sa127 1 1 1 1 1 1 1 128/64 0fe0000?0ffffff 07f0000?07fffff sector address table?s29gl128n (sheet 3 of 3) sector a22?a16 sector size (kbytes/ kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) not recommended for new design
document number: 002-01522 rev. *b page 34 of 92 s29gl512n S29GL256N s29gl128n 7.9 autoselect mode the autoselect mode provides manufacturer and device identificati on, and sector group protection verification, through identifi er codes output on dq7?dq0. this mode is primarily intended for pr ogramming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires vid on address pin a9. address pins a6, a3, a2, a1, and a0 must be as shown in table . in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see table on page 13 ). table on page 34 shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equi pment may then read the corresponding identifier code on dq7? dq0. to access the autoselect codes in-system, the host system can issue the autoselect co mmand via the command register, as shown in table on page 54 and table on page 57 . this method does not require v id . refer to the autoselect command sequence on page 44 for more information. legend l = logic low = v il h = logic high = v ih sa = sector address x = don?t care 7.10 sector protection the device features several levels of sect or protection, which can disable both the program and erase operations in certain sec tors or sector groups: 7.10.1 persistent s ector protection a command sector protection met hod that replaces the old 12 v controlled protection method. autoselect codes (high voltage method) description ce# oe# we# a22t o a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 byte#= v ih byte# = v il manufacturer id : spansion product llhxxv id x l x l l l 00 x 01h device id s29gl512n cycle 1 llhxxv id xl x llh 22 x 7eh cycle 2 h h l 22 x 23h cycle 3 h h h 22 x 01h device id S29GL256N cycle 1 llhxxv id xl x llh 22 x 7eh cycle 2 h h l 22 x 22h cycle 3 h h h 22 x 01h device id s29gl128n cycle 1 llhxxv id xl x llh 22 x 7eh cycle 2 h h l 22 x 21h cycle 3 h h h 22 x 01h sector group protection verification llhsaxv id xl x l h l x x 01h (protected), 00h (unprotected) secured silicon sector indicator bit (dq7), wp# protects highest address sector llhxxv id xl x l h h x x 98h (factory locked), 18h (not factory locked) secured silicon sector indicator bit (dq7), wp# protects lowest address sector llhxxv id xl x l h h x x 88h (factory locked), 08h (not factory locked) not recommended for new design
document number: 002-01522 rev. *b page 35 of 92 s29gl512n S29GL256N s29gl128n 7.10.2 password sector protection a highly sophisticated protection method t hat requires a password before changes to certain sectors or sector groups are permit ted 7.10.3 wp# hardware protection a write protect pin that can pr event program or erase operatio ns in the outermost sectors. the wp# hardware protection feature is always available, independent of the software managed protection method chosen. 7.10.4 selecting a sect or protection mode all parts default to operate in the persistent sector protection mode. the customer must then choose if the persistent or passw ord protection method is most desirable. there are two one-time pr ogrammable non-volatile bits that define which sector protection method is used. if the customer decides to continue using th e persistent sector protecti on method, they must set the persistent sector protection mode locking bit . this permanently sets the part to operate onl y using persistent sect or protection. if the customer decides to use the passw ord method, they must set the password mode locking bit . this permanently sets the part to operate only using password sector protection. it is important to remember that setting either the persistent sector protection mode locking bit or the password mode locking bit permanently selects the protection mode. it is not possible to switch between the two methods once a locking bit is set. it is important that one mode is explicitly selected when th e device is first programmed, rather than relying on the default mode alone. this is so that it is not possible for a system program or virus to later set th e password mode locking bit, which would cause an unexpected shift from the default persistent sect or protection mode into the password protection mode. the device is shipped with all sectors unprotec ted. the factory offers the option of pr ogramming and protecting sectors at the factory prior to shipping the device through the expressflash? service. contact your sales representative for details. it is possible to determine whether a sector is protected or unprotected. see autoselect command sequence on page 44 for details. 7.11 advanced sector protection advanced sector protection features several levels of sector protection, which ca n disable both the progr am and erase operation s in certain sectors. persistent sector protection is a method that replaces the ol d 12v controlled protection method. password sector protection is a highly sophisticated protection method t hat requires a password bef ore changes to certain sectors are permitted. 7.12 lock register the lock register consists of 3 bits (dq2 , dq1, and dq0). these dq2, dq1, dq0 bits of the lock register are programmable by the user. users are not allowed to program bot h dq2 and dq1 bits of the lock register to the 00 state. if the user tries to pro gram dq2 and dq1 bits of the lock register to the 00 state, the device abo rts the lock register back to the default 11 state. the programming time of the lock register is same as the typical wo rd programming time without utili zing the write buffer of the de vice. during a lock register programming sequence execution, the dq6 toggle bit i toggles until the programming of the lock register has completed to indicate programming status. all lock register bits are readable to allow users to verify lock register status es. the customer secured silicon sector protec tion bit is dq0, persistent protection mode lock bit is dq1, and password protection mode lock bit is dq2 are accessible by all users. each of these bits are non-volatile. dq15-dq3 are reserved and must be 1's wh en the user tries to program the dq2, dq1, and dq0 bits of the lock register. the user is not required to prog ram dq2, dq1 and dq0 bits of the lock register at the same time. this allows users to lock the secured silicon sector and then set the device either permanently into password protection mode or persistent protection mode and then lo ck the secured silicon sector at separate instances and time frames. ? secured silicon sector protection allows the user to lock the secured silicon sector area ? persistent protection mode lock bit allows the user to set the de vice permanently to operate in the persistent protection mode ? password protection mode lock bit allows the user to set the device permanently to operate in the password protection mode not recommended for new design
document number: 002-01522 rev. *b page 36 of 92 s29gl512n S29GL256N s29gl128n 7.13 persistent sector protection the persistent sector protection method replaces the old 12 v controlled protection method while at the same time enhancing flexibility by providing three di fferent sector protection states: ? dynamically locked -the sector is protected and ca n be changed by a simple command ? persistently locked -a sector is protected and cannot be changed ? unlocked -the sector is unprotected and can be changed by a simple command in order to achieve these states, three types of ?bits? are going to be used: 7.13.1 dynamic prot ection bit (dyb) a volatile protection bit is assigned for each sector. after powe r-up or hardware reset, the cont ents of all dyb bits are in th e ?unprotected state?. each dyb is individually modifiable thro ugh the dyb set command and dyb clear command. when the parts are first shipped, all of the pe rsistent protect bits (ppb) are cleared into the unprotected state. the dyb bits and ppb lock b it are defaulted to power up in the cleared state or unprot ected state - meaning the all ppb bits are changeable. the protection state for each sector is determined by the logical or of the ppb and the dyb related to that sector. for the sec tors that have the ppb bits cleared, the dyb bits control whether or not the sector is prot ected or unprot ected. by issuing the dyb set and dyb clear command sequences, the dyb bi ts is protected or unprotected, thus pl acing each sector in the protected or unprotected state. these ar e the so-called dynamic locked or unlocked states. they are called dy namic states because it is very easy to switch back and forth between the protected and un-protect ed conditions. this allows soft ware to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. the dyb bits maybe set or cleared as ofte n as needed. the ppb bits allow for a more static, and difficult to change, level of protection. the ppb bits retain their state across power cycles be cause they are non-volatile. indivi dual ppb bits are set with a program command but must all be cleared as a group through an erase command. the ppb lock bit adds an additional le vel of protection. on ce all ppb bits are programmed to the desired sett ings, the ppb lock bit may be set to the ?freeze state?. setting the ppb lock bit to the ?freeze state? disables all program and erase commands to the non- volatile ppb bits. in effect, the ppb lock bi t locks the ppb bits into their current st ate. the only way to clear the ppb lock bit to the ?unfreeze state? is to go through a power cycle, or hardware reset. the software rese t command does not clear the ppb lock bit to the ?unfreeze state?. system boot code can de termine if any changes to the ppb bits are needed e.g. to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock bit to disable any further changes to the ppb bits during system operation. the wp# write protect pin adds a final level of hardware protecti on. when this pin is low it is not possible to change the cont ents of the wp# protected sectors. these sectors ge nerally hold system boot code . so, the wp# pin can prevent any changes to the boot code that could override the choi ces made while setting up sector pr otection during system initialization. it is possible to have sectors that have been persistently lock ed, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dyb set command sequence is all that is necessary. the dyb set and dyb clear commands for the dynami c sectors switch the dyb bits to signify protected and unprotected, respectively. if th ere is a need to change the stat us of the persistently locked sectors, a few more steps are req uired. first, the ppb lock bit must be disabled to the ?unfreeze state? by either putting the device through a power-cycle, or hardwar e reset. the ppb bits can then be changed to reflect the desired settings. setting the ppb lock bit once again to the ?freeze sta te? locks the ppb bits, and the devi ce operates no rmally again. to achieve the best prot ection, execute the ppb lock bit set command early in the boot code, and protect the boot code by holdi ng wp# = v il . lock register dq15-3 dq2 dq1 dq0 don?t care password protection mode lock bit persistent protection mode lock bit secured silicon sector protection bit not recommended for new design
document number: 002-01522 rev. *b page 37 of 92 s29gl512n S29GL256N s29gl128n 7.13.2 persistent protection bit (ppb) a single persistent (non-vo latile) protection bit is assigned to each sector. if a ppb is programmed to the protected state thr ough the ?ppb program? command, that sector is protected from program or erase operations is read-only. if a ppb requires erasure, all o f the sector ppb bits must first be erased in parallel th rough the ?all ppb erase? command. the ?all ppb erase? command preprograms all ppb bits prior to ppb erasing. all ppb bits eras e in parallel, unlike programming where individual ppb bits are programmable. the ppb bits have the same endurance as the flash memory. programming the ppb bit requires the typical word programm ing time without utilizing the write buffer. during a ppb bit programming and all ppb bit erasing sequence executions, the dq6 toggle bit i toggles until the programming of the ppb bit or erasing of all ppb bits has completed to i ndicate programming a nd erasing status. erasing all of the ppb bits at once requires typical sector erase time. during the erasi ng of all ppb bits, the dq3 sector erase time r bit outputs a 1 to indicate the erasu re of all ppb bits are in progress. when the erasure of all ppb bits has completed, the dq3 sect or erase timer bit outputs a 0 to indicat e that all ppb bits have been erased. r eading the ppb status bit requires the initial access time of the device. 7.13.3 persistent protection bit lock (ppb lock bit) a global volatile bit. when set to the ?fr eeze state?, the ppb bits canno t be changed. when cleared to the ?unfreeze state?, th e ppb bits are changeable. there is only one ppb lock bit per device. th e ppb lock bit is cleared to the ?unfreeze state? after power -up or hardware reset. there is no command sequence to unlock or ?unfreeze? the ppb lock bit. configuring the ppb lock bit to the freeze state requires approx imately 100ns. reading the ppb lock status bit requires the ini tial access time of the device. table contains all possible combinations of the dyb bit, ppb bit, and ppb lock bit relating to the status of the sector. in summary, if the ppb bit is set, and the ppb lock bit is set, the sector is protected and the protection cannot be removed until the next power cycle or hardware reset clears the ppb lock bit to ?unfreeze state?. if the ppb bit is cleared, the sector can be dynamically l ocked or unlocked. the dyb bit then controls whether or not the sector is protected or unprotect ed. if the user attemp ts to program or e rase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modified the contents of the protec ted sector. an erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the pr otected sector. the programming of the dyb bit, ppb bit, and ppb lock bit for a given sector c an be verified by writing a dyb status read, ppb status read, and ppb lock status r ead commands to the device. the autoselect sector prot ection verification outputs the or function of the dyb bit and ppb bi t per sector basis. when the or function of the dyb bit and ppb bit is a 1, the sector is either protected by dyb or ppb or bot h. when the or function of the d yb bit and ppb bit is a 0, the sector is u nprotected through both the dyb and ppb. 7.14 persistent protection mode lock bit like the password protection mode lock bit, a persistent protecti on mode lock bit exists to guarantee that the device remain in software sector protection. once programm ed, the persistent protection mode lock bi t prevents programming of the password protection mode lock bit. this guarantees that a hacker coul d not place the device in passw ord protection mode. the password protection mode lock bit resides in the ?lock register?. sector protection schemes protection states sector state dyb bit ppb bit ppb lock bit unprotect unprotect unfreeze unprotected ? ppb and dyb are changeable unprotect unprotect freeze unprotected ? ppb not changeable, dyb is changeable unprotect protect unfreeze protected ? ppb and dyb are changeable unprotect protect freeze protected ? ppb not changeable, dyb is changeable protect unprotect unfreeze protected ? ppb and dyb are changeable protect unprotect freeze protected ? ppb not changeable, dyb is changeable protect protect unfreeze protected ? ppb and dyb are changeable protect protect freeze protected ? ppb not changeable, dyb is changeable not recommended for new design
document number: 002-01522 rev. *b page 38 of 92 s29gl512n S29GL256N s29gl128n 7.15 password sector protection the password sector protection method allows an even higher level of security than the persistent sector protection method. the re are two main differences between the persistent sector protection and the password sector protection methods: ? when the device is first powered on, or comes out of a reset cycl e, the ppb lock bit is set to the locked state, or the freeze state, rather than cleared to the unlocked state, or the unfreeze state. ? the only means to clear and unfreeze the ppb lock bit is by writing a unique 64-bit password to the device. the password sector protection method is otherwise identical to the pers istent sector protection method. a 64-bit password is the only additional tool utilized in this method. the password is stored in a one-time programm able (otp) region outside of the flash me mory. once the password protection mode lock bit is set, the password is permanently set with no means to read, program, or erase it. the password is used to clear and unfreeze the ppb lock bit. the password un lock command must be written to the flash, along with a password. the flash device internally compares the given password wit h the pre-programmed password. if they match, the ppb lock bit is cleared to the unfreezed state , and the ppb bits can be altered. if they do not match, t he flash device does nothing. there is a built-in 2 s delay for each password check after the valid 64-bi t password is entered for the ppb lock bit to be cleared to the ?unfreezed state?. this delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. 7.16 password and password protection mode lock bit in order to select the password sector protection method, the customer must first program the password. the factory recommends that the password be somehow correlated to the unique electronic serial number (esn) of the parti cular flash device. each esn i s different for every flash device; therefore each password should be different for every flash device. while programming in the password region, the customer may perform password read oper ations. once the desired password is programmed in, the customer must then set the password protection m ode lock bit. this operation achieves two objectives: 1. it permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. 2. it also disables all further commands to the passwor d region. all program, and r ead operations are ignored. both of these objectives are im portant, and if not carefully considered, may lead to unrecoverable errors. the user must be sur e that the password sector protection method is desired when programming the password protection mode lock bit. more importantly, the user must be sure t hat the password is correct when the password protec tion mode lock bit is programmed. due to the fact th at read operations are disabled, there is no m eans to read what the password is afterwards. if the password is lost after programm ing the password protection mode lock bit, there is no way to clear and unfreeze the ppb lock bit. the password protection mode lock bit, once programmed, prevents reading the 64-bit pa ssword on the dq bus and further password programming. the password protection mode lock bit is not erasable. once passwo rd protection mode lock bit is programmed, the persistent protection mode lock bit is disabled from programming, guarant eeing that no changes to the protection scheme are allowed. 7.17 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and password read commands. the password function work s in conjunction with the password protection mode lock bit, which when programmed, prevents the password read command from readin g the contents of the passwor d on the pins of the device. 7.18 persistent protecti on bit lock (ppb lock bit) a global volatile bit. the ppb lock bit is a volatile bit that re flects the state of the passwor d protection mode lock bit afte r power-up reset. if the password protection mode lock bit is also programmed after programming the password, the password unlock command must be issued to clear and unf reeze the ppb lock bit after a hardware reset (reset# asse rted) or a power-up reset. successful execution of the pass word unlock command clears a nd unfreezes the ppb lock bit, allo wing for sector ppb bits to be modified. without issuing th e password unlock command, while asserting reset#, taking the dev ice through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a the ?freeze state?. if the password protection mode lock bit is not programmed, the device def aults to persistent protection mode. in the persisten t protection mode, the ppb lo ck bit is cleared to the unfreeze state after power-up or hardware reset. the ppb lock bit is set to the freeze state by issuing the ppb lock bit se t command. once set to the freeze state the only means for clearing the ppb lock bit to not recommended for new design
document number: 002-01522 rev. *b page 39 of 92 s29gl512n S29GL256N s29gl128n the ?unfreeze state? is by issuing a hardware or power-up reset. the password unlock command is ig nored in persistent protectio n mode. reading the ppb lock bit requires a 200ns access time. 7.19 secured silicon sector flash memory region the secured silicon sector feature provides a flash memory regi on that enables permanent part id entification through an electro nic serial number (esn). the secured silicon sector is 256 bytes in length, and uses a secured silicon sector indicator bit (dq7) t o indicate whether or not the secured silicon sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloni ng of a factory locked part. this ensures the security of the esn once the product i s shipped to the field. the factory offers the device with the secured silicon sector ei ther customer lockable (standard shipping option) or factory lo cked (contact an amd sales representative for or dering information). the customer-lockable version is shipped with the secured silic on sector unprotected, allowing customers to program the sector af ter receiving the device. the customer-lockable version also has the secured silicon sector indicator bit permanently set to a 0 . the factory-locked version is always protected when shipped from the factory, and has the secured silicon sect or indicator bit permanently set to a 1 . thus, the secured silicon sector indicator bit prevents customer-lockable devices from being used to replace devices that are factory locked . the secured silicon sector address space in this device is allocated as follows: the system accesses the secured silicon sector through a command sequence (see write protect (wp#) on page 40 ). after the system has written the enter secu red silicon sector command sequence, it may r ead the secured silicon sector by using the addresses normally occupied by the first sector (sa0). this mo de of operation continues until th e system issues the exit secure d silicon sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sendi ng commands to sector sa0. 7.19.1 customer lockable: secured silicon sector not programme d or protected at the factory unless otherwise specified, the device is ship ped such that the customer may program and protect the 256-by te secured silicon sector. the system may program the secured silicon sector using the wr ite-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. see command definitions on page 43 . programming and protecting the secured silicon sector must be us ed with caution since, once protected, there is no procedure available for unprotecting the secured silicon sector area and non e of the bits in the secured si licon sector memory space can be modified in any way. the secured silicon sector area can be prot ected using one of the following procedures: ? write the three-cycle en ter secured silicon se ctor region command. ? to verify the protect/unprotect status of t he secured silicon sector, follow the algorithm. once the secured silicon se ctor is programmed, locked and veri fied, the system must wr ite the exit secured silicon sector regio n command sequence to return to reading and writing within the remainder of the array. secured silicon sector address range customer lockable esn factory locked expressflash factory locked 000000h?000007h determined by customer esn esn or determined by customer 000008h?00007fh unavailable determined by customer not recommended for new design
document number: 002-01522 rev. *b page 40 of 92 s29gl512n S29GL256N s29gl128n 7.19.2 factory locked: secured silicon s ector programmed and protected at the factory in devices with an esn, the secured silicon sector is protecte d when the device is shipped from the factory. the secured silico n sector cannot be modified in any way. an esn factory locked device has an 16-byte random esn at addresses 000000h?000007h. please contact your sales representative for details on ordering esn factory locked devices. customers may opt to have their code programmed by the fa ctory through the expressflash service (express flash factory locked). the devices are then shipped from the factory with the se cured silicon sector permanently locked. contact your sales representative for details on us ing the expressflash service. 7.20 write protect (wp#) the write protect function provides a ha rdware method of protecting the first or last sector group without using v id . write protect is one of two functions provi ded by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the device disables program an d erase functions in the fi rst or last sector group independently of whether those sector groups were pr otected or unprotected usin g the method described in advanced sector protection on page 35 . note that if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is increased. see the table in dc characteristics on page 65 . if the system asserts v ih on the wp#/acc pin, the device reverts to whether th e first or last sector was previously set to be protected or unprotected. note that wp# has an internal pull-up; when unconnected, wp# is at v ih . 7.21 hardware data protection the command sequence requirement of unlock cycles for programming or eras ing provides data protecti on against inadvertent writes (refer to table on page 54 and table on page 57 for command definitions). in add ition, the following hardware data protection measures prevent accidental er asure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. 7.21.1 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper si gnals to the control pins to prevent unintentional writes when v cc is greater than v lko . 7.21.2 write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. 7.21.3 logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. 7.21.4 power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept co mmands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. 8. common flash memory interface (cfi) the common flash interface (cfi) specificat ion outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entir e families of devices. software support can then be device- not recommended for new design
document number: 002-01522 rev. *b page 41 of 92 s29gl512n S29GL256N s29gl128n independent, jedec id-independent, and forward- and backward-compati ble for the specified flash device families. flash vendors can standardize their existing interf aces for long-term compatibility. this device enters the cfi qu ery mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in table , table on page 41 , and table on page 42 . to terminate reading cf i data, the system must write the re set command. the system can also write the cfi query co mmand when the device is in the autosel ect mode. the device en ters the cfi query mode, and the system can read cfi data at the addresses given in table , table , table , and table on page 42 . the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specification an d cfi publication 100, available via the world wide web at htt p:// www.amd.com/flash/cfi. alternatively, contact your sales representative for copies of these documents. cfi query identification string addresses (x16) addresses (x8) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) system interface string addresses (x16) addresses (x8) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0007h typical timeout per single byte/word write 2 n s 20h 40h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0003h max. timeout for byte/word write 2 n times typical 24h 48h 0005h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) not recommended for new design
document number: 002-01522 rev. *b page 42 of 92 s29gl512n S29GL256N s29gl128n device geometry definition addresses (x16) addresses (x8) data description 27h 4eh 001ah 0019h 0018h device size = 2 n byte 1a = 512 mb, 19 = 256 mb, 18 = 128 mb 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0001h number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 00xxh 000xh 0000h 000xh erase block region 1 information (refer to the cfi specification or cfi publication 100) 00ffh, 001h, 0000h, 0002h = 512 mb 00ffh, 0000h, 0000h, 0002h = 256 mb 007fh, 0000h, 0000h, 0002h = 128 mb 31h 32h 33h 34h 62h 64h 66h 68h 0000h 0000h 0000h 0000h erase block region 2 information (refer to cfi publication 100) 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100) primary vendor-specific extended query addresses (x16) addresses (x8) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0033h minor version number, ascii 45h 8ah 0010h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0100b = 110 nm mirrorbit 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0008h sector protect/unprotect scheme 0008h = advanced sector protection 4ah 94h 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv not recommended for new design
document number: 002-01522 rev. *b page 43 of 92 s29gl512n S29GL256N s29gl128n 9. command definitions writing specific address and data commands or sequences into the command register initiates device operations. table on page 54 and table on page 57 define the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place th e device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteristics section for timing diagrams. 9.1 reading array data the device is automatically set to reading array data after devi ce power-up. no commands are required to retrieve data. the dev ice is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device ent ers the erase-suspend-read m ode, after which the system can read data from any non-erase-suspended se ctor. after completing a programming ope ration in the erase suspend mode, the system may once again read arra y data with the same exception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return the device to the r ead (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the autoselect mode. s ee the next section, reset command, for more information. see also requirements for reading array data on page 10 for more information. the read-only operations subsection in the ac characteristics on page 68 section provides the read parameters, and figure 15.1 on page 68 shows the timing diagram. 9.2 reset command writing the reset command resets the device to the read or er ase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, howev er, the device ignores reset commands until the operation is complete. the reset command may be writte n between the sequence cycles in a program command sequence before progra mming begins. this resets the device to the read mode. if the program comma nd sequence is written while the de vice is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be writte n between the sequence cycles in an autoselect co mmand sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the device entered the autoselect mode while in the eras e suspend mode, writing the reset command return s the device to the erase-suspend-read mode. if dq5 goes high during a program or erase o peration, writing the reset command return s the device to the read mode (or erase- suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a write buffer programming oper ation, the system must write the write-to-buffer-abort reset command sequence to reset the device for the next operation. 4fh 9eh 00xxh wp# protection 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h a0h 0001h program suspend 00h = not supported, 01h = supported primary vendor-specific extended query addresses (x16) addresses (x8) data description not recommended for new design
document number: 002-01522 rev. *b page 44 of 92 s29gl512n S29GL256N s29gl128n 9.3 autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. table on page 54 and table on page 57 show the address and data requirements. this method is an alternative to that shown in table on page 34 , which is intended for prom programmers and requires v id on address pin a9. the autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the dev ice is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that c ontains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another au toselect command sequence: ? a read cycle at address xx00h re turns the manufacturer code. ? three read cycles at addresses 01h, 0eh, and 0fh return the device code. ? a read cycle to an address containing a sector address (sa), and the address 02h on a7?a0 in word mode returns 01h if the sector is protected, or 00h if it is unprotected. the system must write the reset comm and to return to the read mode (or erase-suspen d-read mode if the device was previously in erase suspend). 9.4 enter secured silicon sector/exit secured silicon sector command sequence the secured silicon sector region provides a secured data area containing an 8-word/ 16-byte random electronic serial number (esn). the system can access the secured sili con sector region by issuing the three-cy cle enter secured sili con sector command sequence. the device conti nues to access the secured silicon sector region until the system is sues the four-cycle exit secured silicon sector command sequence. the exit secured silicon se ctor command sequence returns the device to normal operation. table on page 54 shows the address and data requirements for both comm and sequences. see also ?sec ured silicon sector flash memory region? for further information. note that the acc function and unlock bypass modes are not available when the secured silicon sector is enabled. 9.5 word program command sequence programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, follow ed by the program set-up command. the program address and data ar e written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provid es internally generated program pulses and verifies the programmed cell margin. table on page 54 and table on page 57 show the address and data requirements for the word program command sequence. when the embedded program algorithm is complete, the device then re turns to the read mode and addresses are no longer latched. the system can determine the status of the program operatio n by using dq7 or dq6. refer to the write oper ation status section f or information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that the secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. programming is allowed in any sequence of address locations and across sector boundaries. programming to the same word address multiple times without intervening erases (incremental bit programming) is permitted. word programming is supported for backward compatibility with existing flash driver software and for occasional writin g of individual words. use of write buffer programming is strongly recommended for general programming use when more than a few words are to be programmed. the effective word programming time using wr ite buffer programming is much shorte r than the single word programming time. any bit cannot be programmed from 0 back to a 1 . attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operat ion was successful. however, a succeedin g read shows that the data is still 0 . only erase operations can convert a 0 to a 1 . not recommended for new design
document number: 002-01522 rev. *b page 45 of 92 s29gl512n S29GL256N s29gl128n 9.5.1 unlock bypass command sequence the unlock bypass feature allows the system to program words to the device fa ster than using the st andard program command sequence. the unlock by pass command sequence is in itiated by first writing two unlock cycles . this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles re quired in the standard program command sequence , resulting in faster total pr ogramming time. table on page 54 and table on page 57 show the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cy cle unlock bypass reset command sequence. (see table on page 54 and table on page 57 ). 9.5.2 write buffer programming write buffer programming allows th e system write to a maximum of 16 words/32 byte s in one programming ope ration. this results i n faster effective programming time than t he standard programming algorithms. the wr ite buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which programming o ccurs. the fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. for example, if the system programs six unique address locations, then 05h should be written to th e device. this tells the device how many write buffer addresses ar e loaded with data and therefore when to expect the program buf fer to flash command. the number of locations to program cannot exceed the size of the write buffer or the operation aborts. the fifth cycle writes the first address location and data to be programmed. the write-buffer-pag e is selected by address bits a max ? a 4 . all subsequent address/data pairs must fa ll within the selected-write-buffer-page. the system then writes the remaining addre ss/ data pairs into the write buffer. write bu ffer locations may be loaded in any order. the write-buffer-page address must be the sa me for all address/data pairs loaded into the write buffer. (this means write buffe r programming cannot be performed across mult iple write-buffer pages. this also means that write buffer programming cannot be performed across multiple se ctors. if the system attemp ts to load programming data outside of the selected writ e-buffer page, t he operation aborts.) note that if a write buffer address location is loaded multiple times, the address/data pair counter is decremented for every d ata load operation. the host system must therefor e account for loading a write-buffer loca tion more than once. the counter decremen ts for each data load operation, not for each unique write-buffer-address location. note al so that if an address location is loaded more than once into the buffer, the final data loaded for that address is programmed. once the specified number of write buffer locations have been loaded, the system must then write the program buffer to flash command at the sector address. any other address and data comb ination aborts the write buffer programming operation. the device then begins programming. data polling should be used while monitoring the last address location loaded into the write bu ffer. dq7, dq6, dq5, and dq1 should be monitored to determi ne the device status during write buffer programming. the write-buffer programmi ng operation can be suspended using the standar d program suspend/resume commands. upon successful completion of the write buffer programming operat ion, the device is ready to execute the next command. the write buffer programming sequence can be aborted in the following ways: ? load a value that is greater than the page buffer size during the number of locations to program step. ? write to an address in a sector different than t he one specified during the write-buffer-load command. ? write an address/data pair to a different write-buffer-page t han the one selected by the starti ng address during the write buff er data loading stage of the operation. ? write data other than the confi rm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the la st address location loaded), dq6 = toggle, and dq5=0. a write-to-buffer-abort reset command sequence must be wr itten to reset th e device for the next operation. write buffer programming is allowed in any sequence. note that the secured silicon sector, autoselect, and cfi functions are unavailable when a program operation is in progress. this flash device is capable of handling multiple write buffer programming operations on the same write buffer address range without intervening erases. any bit in a write buffer address range cannot be programmed from 0 back to a 1 . attempting to do so may cause the device to set dq5 = 1, or cause the dq 7 and dq6 status bits not recommended for new design
document number: 002-01522 rev. *b page 46 of 92 s29gl512n S29GL256N s29gl128n to indicate the operation was successful. however, a succeeding read shows that the data is still 0 . only erase operations can convert a 0 to a 1 . 9.5.3 accelerated program the device offers accelerated prog ram operations through the wp#/a cc pin. when the system asserts v hh on the wp#/acc pin, the device automatically enters the unlock bypass mode. the system may then write the two-cy cle unlock bypass program command sequence. the device uses the higher volta ge on the wp#/acc pin to accelerate the operation. note that the wp#/ acc pin must not be at v hh for operations other than accelerat ed programming, or device damage may result. wp# has an internal pull- up; when unconnected, wp# is at v ih . figure 9.2 on page 48 illustrates the algorithm for the program operation. refer to erase and program operations on page 71 for parameters, and figure 15.4 on page 72 for timing diagrams. not recommended for new design
document number: 002-01522 rev. *b page 47 of 92 s29gl512n S29GL256N s29gl128n figure 9.1 write buffer programming operation notes 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer addres s locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= 1 , then the device failed. if this flow chart location was reached because dq1= 1 , then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write-buffer- programming-abort-reset command. if dq5=1, write the reset command. 4. see table on page 54 and table on page 57 for command sequences required for write buffer programming. write ?write to buffer? command and sector address write number of addresses to progr a m minus 1(wc) and sector address write progr a m buffer to flash sector address write first address/data write to a different sector address fail or abort pa ss read dq15 - dq0 at last loaded address read dq15 - dq0 with address = last loaded address write next address/data pair wc = wc - 1 wc = 0 ? p a rt of ?write to buffer? command sequence ye s ye s ye s ye s ye s ye s no no no no no no abort write to buffer oper ation? dq7 = data? dq7 = data? dq5 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? comm and sequence to return to rea d mode. (note 1) (note 2) (note 3) not recommended for new design
document number: 002-01522 rev. *b page 48 of 92 s29gl512n S29GL256N s29gl128n figure 9.2 program operation note see table on page 54 and table on page 57 for program command sequence. 9.6 program suspend/program resume command sequence the program suspend command allows the system to interrupt a programming operation or a write to buffer programming operation so that data can be read from any non-suspended sector. when the progr am suspend command is written during a programming process, the device halts the program operation within 15 s maximum (5 ? s typical) and updat es the status bits. addresses are not required when writing the program suspend command. after the programming operation is suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program susp end. if a read is needed from th e secured silicon sector area (one-time program area), then user mu st use the proper command sequences to enter and exit this region. note that the secured silicon sector autoselect, and cfi functions are unavailable when program operation is in progress. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device ex its the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence on page 44 for more information. after the program resume command is written, the device revert s to programming. the system c an determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status on page 59 for more information. the system must write the program resume command (address bits are don?t care) to exit the program suspend mode and continue the programming operation. further writes of the resume command are igno red. another program suspend command can be written after the device has resume programming. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress not recommended for new design
document number: 002-01522 rev. *b page 49 of 92 s29gl512n S29GL256N s29gl128n figure 9.3 program suspend/program resume 9.7 chip erase command sequence chip erase is a six bus cycle operation. the chip erase comm and sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional un lock write cycles are th en followed by the chip erase command, which in tu rn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memo ry for an all zero data pattern prio r to electrical erase. the system is not required to provide any controls or timings during these operations. table on page 54 and table on page 57 show the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, the device return s to the read mode and addresses are no longer latched. the system can determine the status of the erase oper ation by using dq7, dq 6, or dq2. refer to write operation status on page 59 for information on these status bits. any commands written during the chip erase operation are ignored, including erase su spend commands. however, note that a hardware reset immediately terminates the erase operati on. if that occurs, the chip erase co mmand sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 9.4 on page 50 illustrates the algorithm for the erase operation. note that the secured silicon sector, autoselect, and cfi functions are unavailable when an erase operation in is progress. refer to erase and program operations on page 71 for parameters, and figure 15.6 on page 73 for timing diagrams. program operation or write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- or program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 s not recommended for new design
document number: 002-01522 rev. *b page 50 of 92 s29gl512n S29GL256N s29gl128n 9.8 sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is init iated by writing two unlock cycles, followe d by a set-up command. two additional unlock cycles are written, and are then followed by the address of the sector to be erased, an d the sector erase command. table on page 54 and table on page 57 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire me mory for an all zero data pattern prior to electrical erase. the system is not required to provide any co ntrols or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading th e sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these a dditional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the la st sector erase co mmand is written. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. note that the secured silicon sector, autoselect, and cfi functions are unavailable when an erase operation in is progress. the system must rewr ite the command sequence and any additional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see dq3: sector erase timer on page 63 .). the time-out begins from the rising edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device return s to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by readi ng dq7, dq6, or dq2 in the erasing sector. refer to the writ e operation status section for information on these status bits. once the sector erase operatio n has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase op eration. if that occurs, the se ctor erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 9.4 illustrates the algorithm for the erase operation. refer to erase and program operations on page 71 for parameters, and figure 15.6 on page 73 for timing diagrams. figure 9.4 erase operation notes 1. see table on page 54 and table on page 57 for program command sequence. 2. see the section on dq3 for information on the sector erase timer. start write era se command sequence (notes 1, 2) data poll to era sing bank from system data = ffh? no ye s era sure completed embedded era se algorithm in progre ss not recommended for new design
document number: 002-01522 rev. *b page 51 of 92 s29gl512n S29GL256N s29gl128n 9.9 erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operat ion and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is writ ten during the sector erase operation, the device requires a typical of 5 ? s ? ?maximum of 20 ? s) to suspend the erase operation. howeve r, when the erase suspend command is wri tten during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation is suspended, the device enters the eras e-suspend-read mode. the system c an read data from or program data to any sector not select ed for erasure. (the device erase suspend s all sectors selected for erasure.) reading at any address within erase-suspended sectors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. after an erase-suspended program operation is complete, th e device returns to the erase-su spend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to write operation status on page 59 for more information. in the erase-suspend-read mode, the system can also i ssue the autoselect command sequence. refer to the autoselect mode on page 34 section and autoselect command sequence on page 44 for details. to resume the sector erase operation, the system must write the erase resume command. the address of the erase-suspended sector is required when writing this co mmand. further writes of the resume command are igno red. another erase suspend command can be written after the chip has resu med erasing. it is important to allow an interval of at least 5 ms between erase resume and erase suspend. 9.10 lock register comm and set definitions the lock register command set permits the user to one-time program the secured silicon sect or protection bit, persistent protection mode lock bit, and password protection mode lock bit. the lock register bits are all readable after an initial acces s delay. the lock register command set entry command sequence must be issued prior to any of the following commands listed, to enable proper command execution. note that issuing the lock register command set entry command disables reads and writes for the flash memory . ? lock register program command ? lock register read command the lock register command set exit command must be issued after the execution of the commands to rese t the device to read mode. otherwise the device hangs. if this happens, the flash device must be reset. please refer to reset# for more information. it is important to note that the device is in either persistent protection mode or pa ssword protection mode depending on the mode selected prior to the device hang. for either the secured silicon sector to be locked, or the device to be permanently set to the persistent protection mode or th e password protection mode, the associated lock register bits must be programmed. note that only the persistent protection mode lock bit or the password protection mode lock bit can be programmed. the lock register program operation aborts if there is an attempt to program both the persistent protection mode and the password protection mode lock bits. the lock register command set exit command must be init iated to re-enable reads and writes to the main memory. not recommended for new design
document number: 002-01522 rev. *b page 52 of 92 s29gl512n S29GL256N s29gl128n 9.11 password protection command set definitions the password protection command set permits the user to program the 64-bit password, verify the programming of the 64-bit password, and then later unlock the device by issuing the valid 64-bit password. the password protection command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the password protection command set entry command disabled reads and writes the main memory. ? password program command ? password read command ? password unlock command the password program command permits programming the password that is used as part of the hardware protection scheme. the actual password is 64-bits long. there is no special addressing order required for programming the password. the password is programmed in 8-bit or 16-bit portions. each portion requires a password program command. once the password is written and verified, t he password protection mode lock bit in the lock register must be programmed in order to prevent verification. the password pr ogram command is only capable of programming 0 s. programming a 1 after a cell is programmed as a 0 results in a time-out by the embedded program algorithm tm with the cell remaining as a 0 . the password is all f?s when shipped from the factory. all 64-bit password combinations are valid as a password. the password read command is used to verify the password. the password is verifiable only when the password protection mode lock bit in the lock register is not programmed. if the password protection mode lock bit in the lock register is programmed and the user attempts to read the password, the dev ice always drives all f?s onto the dq data bus. the lower two address bits (a1?a0) for word mode and (a1?a-1) fo r by byte mode are valid during the password read, password program, and password unlock commands. writing a 1 to any other address bits (a max -a2) aborts the password read and password program commands. the password unlock command is used to clear the ppb lock bit to the unfreeze state so that the ppb bits can be modified. the exact password must be entered in order for the unlocking functi on to occur. this 64-bit password unlock command sequence takes at least 2 s to process each time to prevent a hacker from ru nning through the all 64-bit combinations in an attempt to correc tly match the password. if another password unlock is issued before the 64-bit password check execution window is completed, the command is ignored. if the wrong address or data is given during password unlock command cycle, the device may enter the write- to-buffer abort state. in order to exit the write-to-abort state, the write-to-buffer-abort-reset command must be given. otherw ise the device hangs. the password unlock function is accomplished by writing passwor d unlock command and data to the device to perform the clearing of the ppb lock bit to the unfreeze state . the password is 64 bits long. a1 and a0 are used for matching in word mode and a1, a0, a-1 in byte mode. writing the password unlock command does not need to be address order specific. an example sequence is starting with the lower address a1-a0=00, followed by a1-a0=01, a1 -a0=10, and a1-a0=11 if the device is configured to operate i n word mode. approximately 2 s is required for unlocking the device after the va lid 64-bit password is given to the device. it is the respo nsibility of the microprocessor to keep track of the entering the portions of the 64-bit password with the pa ssword unlock command, the orde r, and when to read the ppb lock bit to conf irm successful passwor d unlock. in order to re-lo ck the device into the password protection mode, the ppb lock bi t set command can be re-issued. note: the password protection command set exit command must be issued after the exec ution of the commands listed previously to reset the device to read mode. otherwise the device hangs. note: issuing the password protection command set exit comman d re-enables reads and writes for the main memory. 9.12 non-volatile sector prot ection command set definitions the non-volatile sector protecti on command set permits t he user to program the pe rsistent protection bits (ppb bits), erase all of the persistent protection bits (ppb bits ), and read the l ogic state of the persistent protection bits (ppb bits). the non-volatile sector prot ection command set entry command sequence must be issued pr ior to any of the commands listed following to enable proper command execution. not recommended for new design
document number: 002-01522 rev. *b page 53 of 92 s29gl512n S29GL256N s29gl128n note that issuing the non-volatile sector protection command set entry command disables reads and writes for the main memory . ? ppb program command the ppb program command is used to program, or set, a given ppb bi t. each ppb bit is individually programmed (but is bulk erased with the other ppb bits). the spec ific sector address (a24-a16 for s29gl5 12n, a23-a16 for S29GL256N, a22-a16 for s29gl128n) is written at the same time as the pr ogram command. if the ppb lock bit is set to the freeze state , the ppb program command does not execute and the comman d times-out without programming the ppb bit. ? all ppb erase command the all ppb erase command is used to erase all ppb bits in bulk. there is no means for individ ually erasing a specific ppb bit. unlike the ppb program, no specific sector ad dress is required. however, when the all ppb erase command is issued, all sector ppb bits are erased in parallel. if the ppb lock bit is set to freeze state , the all ppb erase command does not execute and the command times-out withou t erasing the ppb bits. the device preprograms all ppb bits prior to erasing when issu ing the all ppb erase command. also note that the total number of ppb program/erase cycles has the same endurance as the flash memory array. ? ppb status read command the programming state of the ppb for a given sector can be verified by writing a ppb st atus read command to the device. this requires an initial access time latency. the non-volatile sector pr otection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. note that issuing the non-volatile sector prot ection command set exit command re-enables reads and writes for the main memory . 9.13 global volatile sector protection freeze command set the global volatile se ctor protection freeze command set permits the user to set the ppb lock bit an d reading the l ogic state o f the ppb lock bit. the global volatile sector protection freeze command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. reads and writes from the main memory are not allowed. ? ppb lock bit set command the ppb lock bit set command is used to set the ppb lo ck bit to the freeze state if it is cleared either at reset or if the password unlock command was successfully ex ecuted. there is no ppb lo ck bit clear command. once the ppb lock bit is set to the freeze state , it cannot be cleared unless the device is taken through a power-on clear (for persis tent protection mode) or the password unlock command is executed (for password protec tion mode). if the password protection mode lock bit is programmed, the ppb lock bit status is reflected as set to the freeze state , even after a power-on reset cycle. ? ppb lock bit status read command the programming state of the ppb lock bit can be verified by executing a ppb lock bit status read command to the device. the global volatile sector protection freeze command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. 9.14 volatile sector protection command set the volatile sector protection command set permits t he user to set the dynamic protection bit (dyb) to the protected state , clear the dynamic protection bit (dyb) to the unprotected state , and read the logic state of the dynamic protection bit (dyb). the volatile sector protect ion command set entry command sequence must be issued prior to any of the commands listed following to enable proper command execution. note that issuing the volatile sector protec tion command set entry command disables reads and writes from main memory . ? dyb set command not recommended for new design
document number: 002-01522 rev. *b page 54 of 92 s29gl512n S29GL256N s29gl128n ? dyb clear command the dyb set and dyb clear commands are used to protect or unprot ect a given sector. the high order address bits are issued at the same time as the code 00h or 01h on dq7-dq0. all other dq data bus pins are ignored during the data write cycle. the dyb bits are modifiable at any time, rega rdless of the state of the ppb bit or ppb lo ck bit. the dyb bits are cleared to the unprotected state at power-up or hardware reset. ? dyb status read command the programming state of the dyb bit for a given sector can be ve rified by writing a dyb status read command to the device. this requires an initial access delay. the volatile sector prot ection command set exit command must be issued after the execution of the commands listed previously to reset the device to read mode. note that issuing the volatile sector protection command set exit co mmand re-enables reads and writes to the main memory . 9.15 secured silicon s ector entry command the secured silicon sector entry command a llows the following commands to be executed ? read from secured silicon sector ? program to secured silicon sector once the secured silicon sector entry command is issued, the se cured silicon sector exit comman d has to be issued to exit secured silicon sector mode. 9.16 secured silicon s ector exit command the secured silicon sector exit command may be issued to exit the secured silicon sector mode. 9.17 command definitions memory array commands (x16) command sequence (notes) cycles bus cycles (notes 1 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data asynchronous read (6) 1 ra rd reset (7) 1xxx f0 auto- select manufacturer id 4 555 aa 2aa 55 555 90 x00 01 device id (8) 6 555 aa 2aa 55 555 90 x01 227e x0e data x0f data sector protect verify (9) 4 555 aa 2aa 55 555 90 [sa]x02 data secure device verify (10) ) 4 555 aa 2aa 55 555 90 x03 data cfi query (11) 155 98 program 4 555 aa 2aa 55 555 a0 pa pd write to buffer (12) 6 555 aa 2aa 55 pa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (13) 3 555 aa 2aa 55 555 f0 unlock bypass mode entry 3 555 aa 2aa 55 555 20 program (14) 2 xxx a0 pa pd sector erase (14) 2 xxx 80 sa 30 chip erase (14) 2 xxx 80 sa 10 reset 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 not recommended for new design
document number: 002-01522 rev. *b page 55 of 92 s29gl512n S29GL256N s29gl128n legend x = don?t care. ra = read address. rd = read data. pa = program address. addresses latch on the falling edge of we# or ce# pulse, whichever occurs later. pd = program data. data latches on the rising edge of we# or ce# pulse, whichever occurs first. sa = sector address. any address that falls within a specified sector. see tables ? for sector address ranges. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes 1. see table on page 10 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. 4. address and data bits not specified in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 5. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return reading array data. 6. no unlock or command cycles required when bank is reading array data. 7. reset command is required to return to reading array data in certain cases. see reset command on page 43 for details. 8. data in cycles 5 and 6 are listed in table on page 34 . 9. the data is 00h for an unprotected sector and 01h for a protected sector. ppb status read provides the same data but in inver ted form. 10. if dq7 = 1, region is factory serialized and protected. if dq 7 = 0, region is unserialized and unprotected when shipped from factory. see secured silicon sector flash memory region on page 39 for more information. 11. command is valid when device is ready to read array data or w hen device is in autoselect mode. 12. total number of cycles in the command sequence is determined by the number of words written to the write buffer. 13. command sequence resets device for next command after write-to-buffer operation. 14. requires entry command sequence prior to execution. unlock bypa ss reset command is required to return to reading array data. 15. system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 16. erase resume command is valid only during the erase suspend mode. 17. requires entry command sequence prior to execution. secured si licon sector exit reset command is required to exit this mode; device may otherwise be placed in an unknown state. sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase/program suspend (15) 1xxx b0 erase/program resume (16) 1xxx 30 secured silicon sector entry 3 555 aa 2aa 55 555 88 program (17) 4 555 aa 2aa 55 555 a0 pa pd read (17) 1 00 data exit (17) 4 555 aa 2aa 55 555 90 xxx 00 memory array commands (x16) command sequence (notes) cycles bus cycles (notes 1 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data not recommended for new design
document number: 002-01522 rev. *b page 56 of 92 s29gl512n S29GL256N s29gl128n legend x = don?t care. ra = address of the memory location to be read. sa = sector address. any address that falls within a specified sector. see tables ? for sector address ranges. pwa = password address. address bits a1 and a0 are used to select each 16-bit portion of the 64-bit entity. pwd = password data. rd(0) = dq0 protection indicator bit. if protected, dq0 = 0. if unprotected, dq0 = 1. notes 1. all values are in hexadecimal. 2. shaded cells indicate read cycles. 3. address and data bits not specified in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 4. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 5. entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. no unlock or command cycles required when bank is reading array data. 7. exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. entire two bus-cycle sequence must be entered for each portion of the password. 9. full address range is required for reading password. 10. password may be unlocked or read in any order. un locking requires the full password (all seven cycles). 11. acc must be at v ih when setting ppb or dyb. 12. ?all ppb erase? command pre-programs all ppbs before erasure to prevent over-erasure. sector protection commands (x16) command sequence (notes) cycles bus cycles (notes 1 ? 4 ) first second third fourth fifth sixth seventh addr data addr data addr data addr data add rdata add rdata add rdata lock register bits command set entry (5) 3 555 aa 2aa 55 555 40 program (6) 2xx a0 xxx data read (6) 1 00 data command set exit (7) 2xx 90 xx 00 password protection command set entry (5) 3 555 aa 2aa 55 555 60 program (8) 2xx a0pwaxpwdx read (9) 4 xxx pwd 0 01 pwd1 02 pwd 2 03 pwd 3 unlock (10) 700 25 00 03 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 00 29 command set exit (7) 2xx 90 xx 00 non-volatile sector protection (ppb) command set entry (5) 3 555 aa 2aa 55 555 c0 ppb program (11) 2xx a0 sa 00 all ppb erase ( 11 , 12 ) 2 xx 80 00 30 ppb status read 1 sa rd(0) command set exit (7) 2xx 90 xx 00 global volatile sector protection freeze (ppb lock) command set entry (5) 3 555 aa 2aa 55 555 50 ppb lock bit set 2 xx a0 xx 00 ppb lock bit status read 1 xxx rd(0) command set exit (7) 2xx 90 xx 00 volatile sector protection (dyb) command set entry (5) 3 555 aa 2aa 55 555 e0 dyb set 2 xx a0 sa 00 dyb clear 2 xx a0 sa 01 dyb status read 1 sa rd(0) command set exit (7) 2xx 90 xx 00 not recommended for new design
document number: 002-01522 rev. *b page 57 of 92 s29gl512n S29GL256N s29gl128n legend x = don?t care. ra = read address. rd = read data. pa = program address. addresses latch on the falling edge of we# or ce# pulse, whichever occurs later. pd = program data. data latches on the rising edge of we# or ce# pulse, whichever occurs first. sa = sector address. any address that falls within a specified sector. see tables ? for sector address ranges. wbl = write buffer location. address must be within the same write buffer page as pa. wc = word count. number of write buffer locations to load minus 1. notes 1. see table on page 10 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. 4. address and data bits not specified in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 5. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return reading array data. 6. no unlock or command cycles required when bank is reading array data. 7. reset command is required to return to reading array data in certain cases. see reset command on page 43 for details. 8. data in cycles 5 and 6 are listed in table on page 34 . 9. the data is 00h for an unprotected sector and 01h for a protected sector. ppb status read provides the same data but in inver ted form. 10. if dq7 = 1, region is factory serialized and protected. if dq 7 = 0, region is unserialized and unprotected when shipped from factory. see secured silicon sector flash memory region on page 39 for more information. 11. command is valid when device is ready to read array data or w hen device is in autoselect mode. 12. total number of cycles in the command sequence is determined by the number of words written to the write buffer. 13. command sequence resets device for next command after write-to-buffer operation. 14. requires entry command sequence prior to execution. unlock bypa ss reset command is required to return to reading array data. memory array commands (x8) command sequence (notes) cycles bus cycles (notes 1 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data asynchronous read (6) 1ra rd reset (7) 1xxx f0 auto- select manufacturer id 4 aaa aa 555 55 aaa 90 x00 01 device id (8) 6 aaa aa 555 55 aaa 90 x02 xx7e x1c data x1e data sector protect verify (9) 4 aaa aa 555 55 aaa 90 [sa]x04 data secure device verify (10) 4 aaa aa 555 55 aaa 90 x06 data cfi query (11) 1aa 98 program 4 aaa aa 555 55 aaa a0 pa pd write to buffer (12) 6 aaa aa 555 55 pa 25 sa wc pa pd wbl pd program buffer to flash 1 sa 29 write to buffer abort reset (13) 3 aaa aa pa 55 555 f0 unlock bypass mode entry 3 aaa aa 555 55 aaa 20 program (14) 2 xxx a0 pa pd sector erase (14) 2 xxx 80 sa 30 chip erase (14) 2 xxx 80 sa 10 reset 2 xxx 90 xxx 00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 erase/program suspend (15) 1xxx b0 erase/program resume (16) 1xxx 30 secured silicon sector entry 3 aaa aa 555 55 aaa 88 program (17) 4 aaa aa 555 55 aaa a0 pa pd read (17) 100data exit (17) 4 aaa aa 555 55 aaa 90 xxx 00 not recommended for new design
document number: 002-01522 rev. *b page 58 of 92 s29gl512n S29GL256N s29gl128n 15. system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 16. erase resume command is valid only during the erase suspend mode. 17. requires entry command sequence prior to execution. secured si licon sector exit reset command is required to exit this mode; device may otherwise be placed in an unknown state. legend x = don?t care. ra = address of the memory location to be read. sa = sector address. any address that falls within a specified sector. see tables ? for sector address ranges. pwa = password address. address bits a1 and a0 are used to select each 16-bit portion of the 64-bit entity. pwd = password data. rd(0) = dq0 protection indicator bit. if protected, dq0 = 0. if unprotected, dq0 = 1. notes 1. all values are in hexadecimal. 2. shaded cells indicate read cycles. 3. address and data bits not specified in table, legend, or notes are don?t cares (each hex digit implies 4 bits of data). 4. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. the system must write the reset command to return the device to reading array data. 5. entry commands are required to enter a specific mode to enable instructions only available within that mode. sector protection commands (x8) command sequence (notes) cycles bus cycles (notes 1 ? 4 ) 1st/8th 2nd/9th 3rd/10th 4th/11th 5th 6th 7th addr data addr data addr data addr data add rdata add rdata add rdata lock register bits command set entry (5) 3 aaa aa 555 55 aaa 40 program (6) 2 xxx a0 xxx data read (6) 1 00 data command set exit (7) 2 xxx 90 xxx 00 password protection command set entry (5) 3 aaa aa 555 55 aaa 60 program (8) 2 xxx a0 pwax pwdx read (9) 8 00 pwd 0 01 pwd1 02 pwd 2 03 pwd 3 04 pwd 4 05 pwd 5 06 pwd 6 07 pwd 7 unlock (10) 1 1 00 25 00 03 00 pwd 0 01 pwd 1 02 pwd 2 03 pwd 3 04 pwd 4 05 pwd 5 06 pwd6 07 pwd 7 00 29 command set exit (7) 2xx 90 xx 00 non-volatile sector protection (ppb) command set entry (5) 3 aaa aa 555 55 aaa c0 ppb program (11) 2 xxx a0 sa 00 all ppb erase ( 11 , 12 )2xxx80 00 30 ppb status read 1 sa rd(0) command set exit (7) 2 xxx 90 xxx 00 global volatile sector protection freeze (ppb lock) command set entry (5) 3 aaa aa 555 55 aaa 50 ppb lock bit set 2 xxx a0 xxx 00 ppb lock bit status read 1 xxx rd(0) command set exit (7) 2 xxx 90 xx 00 volatile sector protection (dyb) command set entry (5) 3 aaa aa 555 55 aaa e0 dyb set 2 xxx a0 sa 00 dyb clear 2 xxx a0 sa 01 dyb status read 1 sa rd(0) command set exit (7) 2 xxx 90 xxx 00 not recommended for new design
document number: 002-01522 rev. *b page 59 of 92 s29gl512n S29GL256N s29gl128n 6. no unlock or command cycles required when bank is reading array data. 7. exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. entire two bus-cycle sequence must be entered for each portion of the password. 9. full address range is required for reading password. 10. password may be unlocked or read in any order. un locking requires the full password (all seven cycles). 11. acc must be at v ih when setting ppb or dyb. 12. ?all ppb erase? command pre-programs all ppbs before erasure to prevent over-erasure. 10. write operation status the device provides several bits to dete rmine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table on page 63 and the following subsections describe the function of thes e bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is co mplete or in progress. the device also provides a hardware-ba sed output signal, ry/ by#, to determine whether an embedded program or erase operation is in progress or is completed. 10.1 dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid afte r the rising edge of the final we# pulse in th e command sequence. during the embedded program algorithm, the device outputs on dq 7 the complement of the datum programmed to dq7. this dq7 status also applies to programming durin g erase suspend. when the embedded program al gorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, dat a# polling on dq7 is active for approximately 1 s, then the device returns to the read mode. during the embedded erase algorit hm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspe nd mode, data# polling produces a 1 on dq7. the system must provide an address within any of the sectors selected for erasure to re ad valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active f or approximately 100 s, then the device returns to the read mo de. if not all selected sectors ar e protected, the embedded erase algorithm erases the unprote cted sectors, and ignores the selected se ctors that are protected. howe ver, if the system reads dq7 at an address within a protected sect or, the status may not be valid. just prior to the completion of an embedded program or eras e operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the dev ice has completed the program or erase operation and dq7 has valid data, the data out puts on dq0?dq6 may be still in valid. valid data on dq0?dq7 appears on successive read cycles. table on page 63 shows the outputs for data# polling on dq7. figure 10.1 on page 60 shows the data# polling algorithm. figure 15.4 on page 72 shows the data# polling timing diagram. not recommended for new design
document number: 002-01522 rev. *b page 60 of 92 s29gl512n S29GL256N s29gl128n figure 10.1 data# polling algorithm notes 1. va = valid address for programming. during a sector erase operat ion, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-prot ected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 10.2 ry/by#: ready/busy# the ry/by# is a dedicated, open- drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid af ter the rising edge of the final we# pulse in the co mmand sequence. since ry/by# is an open-drain outp ut, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mod e.) if the output is high (ready), the devic e is in the read mode, the standby mo de, or in the erase-suspend-read mode. table on page 63 shows the outputs for ry/by#. 10.3 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we # pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algor ithm operation, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are pr otected, dq6 toggles for approximately 10 0 s, then returns to reading array data. if not all selected sectors are pr otected, the embedded erase al gorithm erases the unprotec ted sectors, and ignores the selected sectors that are protected. dq7 = data? ye s no no dq5 = 1 no ye s ye s fail pass read dq15?dq0 addr = va read dq15?dq0 addr = va dq7 = data? start not recommended for new design
document number: 002-01522 rev. *b page 61 of 92 s29gl512n S29GL256N s29gl128n the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the em bedded erase algorithm is in progress), dq6 toggles. when the device enters the eras e suspend mode, dq6 stops toggling. however, the system must al so use dq2 to determine which sectors are erasing or erase- suspended. alternat ively, the system can use dq7 (see the subsection on dq 7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspen d-program mode, and stops toggling once th e embedded program algorithm is complete. table on page 63 shows the outputs for toggle bit i on dq6. figure 10.2 shows the toggle bit algorithm. figure 15.8 on page 74 shows the toggle bit timing diagrams. figure 15.9 on page 74 shows the differences between dq 2 and dq6 in graphical form. see also dq2: toggle bit ii on page 62 . figure 10.2 toggle bit algorithm note the system should recheck the toggle bit even if dq5 = 1 because the toggle bit may stop toggling as dq5 changes to 1. see the subsections on dq6 and dq2 for more information. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 not recommended for new design
document number: 002-01522 rev. *b page 62 of 92 s29gl512n S29GL256N s29gl128n 10.4 dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indica tes whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is eras e-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addre sses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase- suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in er ase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table on page 63 to compare outputs for dq2 and dq6. figure 10.2 on page 61 shows the toggle bit algorithm in flowchart form, and the section dq2: toggle bit ii on page 62 explains the algorithm. see also the ry/by#: ready/busy# on page 60 . figure 15.8 on page 74 shows the toggle bit timing diagram. figure 15.9 on page 74 shows the differences between dq2 and dq6 in graphical form. 10.5 reading toggle bits dq6/dq2 refer to figure 10.2 on page 61 and figure 15.9 on page 74 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq7?d q0 at least twice in a row to determine whether a toggle bit is toggling. typicall y, the system would note and store the va lue of the toggle bit after t he first read. after the second read, the system would compare t he new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operat ion. the system can read array data on dq7?dq0 on t he following read cycle. however, if after the initial two read cycles, the system det ermines that the toggle bit is still toggling, the system also sho uld note whether the value of dq5 is high (see the section on dq5). if it is, the system sh ould then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bi t is no longer toggling, the de vice has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation succ essfully, and the system must write the reset co mmand to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the s ystem may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previ ous paragraph. alternat ively, it may choose to per form other system tasks. in th is case, the system must st art at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 10.2 on page 61 ). 10.6 dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer ti me has exceeded a specified inter nal pulse count limit. under th ese conditions dq5 produces a 1 , indicating that the program or er ase cycle was not succe ssfully completed. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0 . only an erase operation can change a 0 back to a 1 . under this condition, the device halts t he operation, and when the timing limit is exceeded, dq5 produces a 1 . in all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend- read if the device was previously in the erase-suspend-program mode). not recommended for new design
document number: 002-01522 rev. *b page 63 of 92 s29gl512n S29GL256N s29gl128n 10.7 dq3: sector erase timer after writing a sector erase command seque nce, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-o ut also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a 0 to a 1 . if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also sector erase command sequence on page 50 . after the sector erase command is written, the system should read the status of dq7 (data# pollin g) or dq6 (toggle bit i) to en sure that the device has accepted the command s equence, and then read dq3. if dq3 is 1 , the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is 0 , the device accepts additional sector erase commands . to ensure the command is acce pted, the system software should check the status of dq3 prior to and following each subsequent sector er ase command. if dq3 is high on the second status check, the last command might not have been accepted. table on page 63 shows the status of dq3 relati ve to the other status bits. 10.8 dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation wa s aborted. under these cond itions dq1 produces a 1 . the system must issue the write-to-buffer-abort-reset command sequence to return the device to reading array data. see write buffer on page 11 for more details. notes 1. dq5 switches to 1 when an embedded program, embedded erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the se ction on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status info rmation. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to 1 when the device has aborted the write-to-buffer operation write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 0 abort (note 4) dq7# toggle 0 n/a n/a 1 0 not recommended for new design
document number: 002-01522 rev. *b page 64 of 92 s29gl512n S29GL256N s29gl128n 11. absolute maximum ratings notes 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 11.1 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 11.2 . 2. minimum dc input voltage on pins a9 and acc is ?0.5 v. during voltage transitions, a9 and acc may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 11.1 . maximum dc input voltage on pin a9 and acc is +12.5 v wh ich may overshoot to +14.0v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. ex posure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 11.1 maximum negative overshoot waveform figure 11.2 maximum positive overshoot waveform storage temperature, plastic packages ?65c to +150c ambient temperature with power applied ?65c to +125c voltage with respect to ground: v cc (note 1) ?0.5 v to +4.0 v v io ?0.5 v to +4.0 v a9 and acc (note 2) ?0.5 v to +12.5 v all other pins (note 1) ?0.5 v to v cc + 0.5v output short circuit current (note 3) 200 ma 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v not recommended for new design
document number: 002-01522 rev. *b page 65 of 92 s29gl512n S29GL256N s29gl128n 12. operating ranges industrial (i) devices ambient temperature (t a ) ?40c to +85c supply voltages v cc +2.7 v to +3.6 v or +3.0 v to 3.6 v v io (note 2) +1.65 v to 1.95 v or v cc notes 1. operating ranges define those limits between which the functionality of the device is guaranteed. 2. see product selector guide on page 4 . 13. dc characteristics 13.1 cmos compatible parameter symbol parameter description (notes) test conditions min typ max unit i li input load current (1) v in = v ss to v cc , v cc = v cc max wp/acc: 2.0 a others: 1.0 i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (1) ce# = v il ; oe# = v ih , v cc = v ccmax ; f = 1 mhz, byte mode 620 ma ce# = v il ; oe# = v ih , v cc = v ccmax ; f = 5 mhz, word mode 30 50 ce# = v il ; oe# = v ih , v cc = v ccmax ; f = 10 mhz 60 90 i cc2 v cc intra-page read current (1) ce# = v il ; oe# = v ih, v cc = v ccmax ; f = 10 mhz 110 ma ce# = v il , oe# = v ih , v cc = v ccmax ; f=33 mhz 520 i cc3 v cc active erase/program current ( 2 , 3 ) ce# = v il, oe# = v ih, v cc = v ccmax 50 90 ma i cc4 v cc standby current v cc = v ccmax ; v io = v cc ; oe# = v ih ; v il = v ss + 0.3 v / ?0.1 v; ce#, reset# = v cc 0.3 v 15a i cc5 v cc reset current v cc = v ccmax ; v io = v cc ; v il = v ss + 0.3 v / ?0.1 v; reset# = v ss 0.3 v 15a i cc6 automatic sleep mode (4) v cc = v ccmax ; v io = v cc ; v ih = v cc 0.3 v; v il = v ss + 0.3 v / ?0.1 v; wp#/a cc = v ih 15 a i acc acc accelerated program current ce# = v il, oe# = v ih, v cc = v ccmax, wp#/acc = v ih wp#/ acc pin 10 20 ma v cc pin 50 90 v il input low voltage (5) ?0.1 0.3 x v io v v ih input high voltage (5) 0.7 x v io v io + 0.3 v v hh voltage for acc erase/program acceleration v cc = 2.7?3.6 v 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7?3.6 v 11.5 12.5 v not recommended for new design
document number: 002-01522 rev. *b page 66 of 92 s29gl512n S29GL256N s29gl128n notes 1. the i cc current listed is typically le ss than 2 ma/mhz, with oe# at v ih . 2. i cc active while embedded erase or embedded program or write buffer programming is in progress. 3. not 100% tested. 4. automatic sleep mode enables the lower power mode when addresses remain stable tor t acc + 30 ns. 5. v io = 1.65?1.95 v or 2.7?3.6 v 6. v cc = 3 v and v io = 3v or 1.8v. when v io is at 1.8v, i/o pins cannot operate at 3v. 14. test conditions figure 14.1 test setup note diodes are in3064 or equivalent note if v io < v cc , the reference level is 0.5 v io . v ol output low voltage (5) i ol = 100 a 0.15 x v io v v oh output high voltage (5) i oh = -100 a 0.85 x v io v v lko low v cc lock-out voltage (3) 2.3 2.5 v test specifications test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?v io v input timing measurement reference levels (see note) 0.5v io v output timing measurement reference levels 0.5 v io v parameter symbol parameter description (notes) test conditions min typ max unit 2.7 k ? c l 6.2 k ? 3.3 v device under te s t not recommended for new design
document number: 002-01522 rev. *b page 67 of 92 s29gl512n S29GL256N s29gl128n 14.1 key to switching waveforms figure 14.2 input waveforms and measurement levels note if v io < v cc , the input measurement reference level is 0.5 v io . waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) v io 0.0 v 0.5 v io 0.5 v io v output measu rement level input not recommended for new design
document number: 002-01522 rev. *b page 68 of 92 s29gl512n S29GL256N s29gl128n 15. ac characteristics 15.1 read-only operations notes 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 14.1 on page 66 and table on page 66 for test specifications. 5. unless otherwise indicated, ac specifications for 90 ns, 100 ns, and 110 ns speed options are tested with v io = v cc = 3 v. ac specifications for 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. 6. 90 ns speed option only applicable to s29gl128n and S29GL256N. figure 15.1 read operation timings parameter description test setup speed options jedec std. 90 (note 6) 100 110 110 unit t avav t rc read cycle time v io = v cc = 3 v min 90 100 110 ns v io = 1.8 v, v cc = 3 v 110 t avqv t acc address to output delay (note 2) v io = v cc = 3 v max 90 100 110 ns v io = 1.8 v, v cc = 3 v 110 t elqv t ce chip enable to output delay (note 3) v io = v cc = 3 v max 90 100 110 ns v io = 1.8 v, v cc = 3 v 110 t pacc page access time max 25 25 25 30 ns t glqv t oe output enable to output delay max 25 25 35 35 ns t ehqz t df chip enable to output high z (note 1) max 20 ns t ghqz t df output enable to output high z (note 1) max 20 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t ceh chip enable hold time read min 35 ns t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df t ceh not recommended for new design
document number: 002-01522 rev. *b page 69 of 92 s29gl512n S29GL256N s29gl128n figure 15.2 page read timings note * figure shows word mode. addresses are a2?a-1 for byte mode. 15.2 hardware reset (reset#) notes 1. not 100% tested. if ramp rate is equal to or faster than 1v/100s with a falling edge of the reset# pin initiated, the reset# pin needs to be held low only for 100s for power-up. 2. next generation devices may have different reset speeds. to increase system design considerations, please refer to advance information on s29gl-p hardware reset (reset#) and power-up sequence on page 80 for advance reset spee ds on s29gl-p devices. parameter description speed (note 2) unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (note 1) max 20 ns t ready reset# pin low (not during embedded algorithms) to read mode (note 1) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (note 1) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns amax - a2 ce# oe# a2 - a0* data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c not recommended for new design
document number: 002-01522 rev. *b page 70 of 92 s29gl512n S29GL256N s29gl128n figure 15.3 reset timings reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb t rh not recommended for new design
document number: 002-01522 rev. *b page 71 of 92 s29gl512n S29GL256N s29gl128n 15.3 erase and program operations notes 1. not 100% tested. 2. see erase and programming performance on page 77 for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is ba sed upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 90 ns, 100 ns, and 110 ns speed options are tested with v io = v cc = 3 v. ac specifications for 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. 6. 90 ns speed option only applicable to s29gl128n and S29GL256N. parameter speed options jedec std. description 90 (note 6) 100 110 110 unit t avav t wc write cycle time (note 1) min 90 100 110 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2 , 3 ) typ 240 s effective write buffer program operation (notes 2 , 4 ) per word typ s 15 accelerated effective write buffer program operation (notes 2 , 4 ) per word typ s 13.5 program operation (note 2) word typ s 60 accelerated programming operation (note 2) word typ s 54 t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s t busy erase/program valid to ry/by# delay max 90 ns not recommended for new design
document number: 002-01522 rev. *b page 72 of 92 s29gl512n S29GL256N s29gl128n figure 15.4 program operation timings notes 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode. figure 15.5 accelerated program timing diagram notes 1. not 100% tested. 2. ce#, oe# = v il 3. oe# = v il 4. see figure 14.1 on page 66 and table on page 66 for test specifications. oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa acc t vhh v hh v il or v ih v il or v ih t vhh not recommended for new design
document number: 002-01522 rev. *b page 73 of 92 s29gl512n S29GL256N s29gl128n figure 15.6 chip/sector erase operation timings notes 1. sa = sector address (for sector erase), va = valid address for reading status data (see write operation status on page 59 ). 2. these waveforms are for the word mode. figure 15.7 data# polling timings (during embedded algorithms) notes 1. va = valid address. illustration shows first status cycle afte r command sequence, last status read cycle, and array data read cycle. 2. t oe for data polling is 45 ns when v io = 1.65 to 2.7 v and is 35 ns when v io = 2.7 to 3.6 v. oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy we# ce# oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc not recommended for new design
document number: 002-01522 rev. *b page 74 of 92 s29gl512n S29GL256N s29gl128n figure 15.8 toggle bit timings (during embedded algorithms) notes va = valid address; not required for dq6. illustration shows firs t two status cycle after command sequence, last status read cy cle, and array data read cycle figure 15.9 dq2 vs. dq6 note dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq2 and dq6 valid data valid status valid status valid status ry/by# enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing not recommended for new design
document number: 002-01522 rev. *b page 75 of 92 s29gl512n S29GL256N s29gl128n 15.4 alternate ce# controlled erase and program operations: s29gl128n, S29GL256N, s29gl512n notes 1. not 100% tested. 2. see ac characteristics on page 68 for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is ba sed upon a 16-word/32-byte write buffer operation. 5. unless otherwise indicated, ac specifications for 90 ns, 100ns, and 110 ns speed options are tested with v io = v cc = 3 v. ac specifications for 110 ns speed options are tested with v io = 1.8 v and v cc = 3.0 v. 6. 90 ns speed option only applicable to s29gl128n and S29GL256N. parameter speed options jedec std. description 90 (note 6) 100 110 110 unit t avav t wc write cycle time (note 1) min 90 100 110 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t elax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling min 20 ns t oeph oe# high during toggle bit polling min 20 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2 , 3 ) typ 240 s effective write buffer program operation (notes 2 , 4 ) per word typ 15 s effective accelerated write buffer program operation (notes 2 , 4 ) per word typ 13.5 s program operation (note 2) word typ 60 s accelerated programming operation (note 2) word typ 54 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec not recommended for new design
document number: 002-01522 rev. *b page 76 of 92 s29gl512n S29GL256N s29gl128n figure 15.10 alternate ce# controlled write (erase/program) operation timings notes 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy not recommended for new design
document number: 002-01522 rev. *b page 77 of 92 s29gl512n S29GL256N s29gl128n 16. erase and programming performance notes 1. typical program and erase times assume the following conditions: 25c, 3.0 v v cc , 10,000 cycles, checkerboard pattern. 2. under worst case conditions of 90c, v cc = 3.0 v, 100,000 cycles. 3. effective write buffer specification is based upon a 16-word write buffer operation. 4. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table on page 54 and table on page 57 for further information on command definitions. 17. tsop pin and bga package capacitance notes 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 3.5 sec excludes 00h programming prior to erasure (note 4) chip erase time s29gl128n 64 256 sec S29GL256N 128 512 s29gl512n 256 1024 total write buffer programming time (note 3) 240 s excludes system level overhead (note 5) total accelerated effective write buffer programming time (note 3) 200 s chip program time s29gl128n 123 sec S29GL256N 246 s29gl512n 492 parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf bga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf bga 3.9 4.7 pf not recommended for new design
document number: 002-01522 rev. *b page 78 of 92 s29gl512n S29GL256N s29gl128n 18. physical dimensions 18.1 ts056?56-pin standard thin small outline package (tsop) notes: 1 controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982.) 2 pin 1 identifier for standard pin out (die up). 3 to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 4 dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15 mm per side. 5 dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 mm total in excess of b dimension at max material condition. minimum space between protrusion and an adjacent lead to be 0.07 mm. 6 these dimesions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 7 lead coplanarity shall be within 0.10 mm as measured from the seating plane. 8 dimension "e" is measured at the centerline of the leads. 3160\38.10a mo-142 (b) ec ts 56 nom. --- --- 1.00 1.20 0.15 1.05 max. --- min. 0.95 0.20 0.23 0.17 0.22 0.27 0.17 --- 0.16 0.10 --- 0.21 0.10 20.00 20.20 19.80 14.00 14.10 13.90 0.60 0.70 0.50 -8? 0? --- 0.20 0.08 56 18.40 18.50 18.30 0.05 0.50 basic e r b1 jedec package symbol a a2 a1 d1 d c1 c b e l n o not recommended for new design
document number: 002-01522 rev. *b page 79 of 92 s29gl512n S29GL256N s29gl128n 18.2 laa064?64-ball fortifie d ball grid array (fbga) 3354 \ 16-038.12d package laa 064 jedec n/a 13.00 mm x 11.00 mm package symbol min nom max note a --- --- 1.40 profile height a1 0.40 --- --- standoff a2 0.60 --- --- body thickness d 13.00 bsc. body size e 11.00 bsc. body size d1 7.00 bsc. matrix footprint e1 7.00 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 64 ball count b 0.50 0.60 0.70 ball diameter ed 1.00 bsc. ball pitch - d direction ee 1.00 bsc. ball pitch - e direction sd / se 0.50 bsc. solder ball placement none depopulated solder balls notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. not recommended for new design
document number: 002-01522 rev. *b page 80 of 92 s29gl512n S29GL256N s29gl128n 19. advance information on s29gl-p ha rdware reset (reset#) and power- up sequence note ce#, oe# and we# must be at logic high during reset time. figure 19.1 reset timings hardware reset (reset#) parameter description speed unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode or write mode min 35 s t ready reset# pin low (not during embedded algorithms) to read mode or write mode min 35 s t rp reset# pulse width min 35 s t rh reset high time before read min 200 ns t rpd reset# low to standby mode min 10 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb t rh not recommended for new design
document number: 002-01522 rev. *b page 81 of 92 s29gl512n S29GL256N s29gl128n notes 1. v io < v cc + 200 mv. 2. v io and v cc ramp must be in sync during power up. if reset# is not stabl e for 35 s, the following conditions may occur: the device does n ot permit any read and write operations, valid read operations return ffh, and a hardware reset is required. 3. maximum v cc power up current is 20 ma (reset# =v il ). figure 19.2 power-on reset timings power-up sequence timings parameter description speed unit t vcs reset low time from rising edge of v cc (or last reset pulse) to rising edge of reset# min 35 s t vios reset low time from rising edge of v io (or last reset pulse) to rising edge of reset# min 35 s t rh reset high time before read max 200 ns ce# reset# t rh v vcc_min v vio_min t vcs t vios cc io not recommended for new design
document number: 002-01522 rev. *b page 82 of 92 s29gl512n S29GL256N s29gl128n 20. advance information on s29g l-r 65 nm mirrorbit hardware reset (reset#) and p ower-up sequence note ce#, oe# and we# must be at logic high during reset time. figure 20.1 reset timings note the sum of t rp and t rh must be equal to or greater than t rph . notes 1. v io < v cc + 200 mv. 2. v io and v cc ramp must be in sync during power-up. if reset# is not stable for 300 s, the following condi tions may occur: the device does not permit any read and write operations, valid read operations return ffh, and a hardware reset is required. 3. maximum v cc power up current is 20 ma (reset# =v il ). hardware reset (reset#) parameter description limit time unit t rph reset# low to ce# low min 35 s t rp reset# pulse width min 200 ns t rh time between reset# (high) and ce# (low) min 200 ns power-up sequence timings parameter description limit time unit t vcs v cc setup time to first access min 300 s t vios v io setup time to first access min 300 s t rph reset# low to ce# low min 35 s t rp reset# pulse width min 200 ns t rh time between reset# (high) and ce# (low) min 200 ns t rph ce# reset# t rp t rh not recommended for new design
document number: 002-01522 rev. *b page 83 of 92 s29gl512n S29GL256N s29gl128n figure 20.2 power-on reset timings note the sum of t rp and t rh must be equal to or greater than t rph . ce# v cc v io r eset# t vios t vcs t rp t rh t rph not recommended for new design
document number: 002-01522 rev. *b page 84 of 92 s29gl512n S29GL256N s29gl128n 21. document history page document title:s29gl512n , S29GL256N, s29gl128n 512, 256, 128 mbit, 3 v, page flash featuring 110 nm mirrorbit document number: 002-01522 rev. ecn no. orig. of change submission date description of change ** - rysu 09/03/2003 a:initial release spansion publication number: s29gl-n_00 ** - rysu 10/16/2003 a1:global added laa064 package. distinctive characteristics, performance characteristics clarified fifth bullet information. added rtsop to package options. distinctive characteristics, software and hardware features clarified password sector protection to advanced sector protection connection diagrams removed note. ordering information modified package codes device bus operations, table 1 modified table, removed note. sector address tables all address ranges doubled in all sector address tables. sector protection lock register: corrected text to reflect 3 bits instead of 4. table 6, lock register: corrected address range from dq15-5 to dq15-3; removed dq4 and dq3; corrected dq15-3 lock register to don?t care. table 7, sector protection sc hemes: corrected sector states. command definitions table 12, command definitions, x16 nonvolatile sector protection comm and set entry second cycle address corrected from 55 to 2aa. legend: clarified pwdx, data notes: clarified note 19. table 13, command definitions, x8 password read and unlock addresses and data corrected. legend: clarified pwdx, data notes: clarified note 19. test conditions table test specificatio ns and figure input wave forms and measurement levels: corrected input pulse levels to 0.0?vio; corrected input timing measurement reference levels to 0.5vio. not recommended for new design
document number: 002-01522 rev. *b page 85 of 92 s29gl512n S29GL256N s29gl128n ** - rysu 01/22/2004 a2 : lock register corrected and added new text for secured silicon sector protection bit, persistent protection mode lock bit, and password protection mode lock bit. persistent sector protection persistent protection bit (ppb): added the second paragraph text about programming the ppb bit. persistent protection bit lock (ppb lo ck bit): added the second paragraph text about configuring the ppb lock bit, and fourth paragraph on autoselect sector protection verification. added ppb lock bit requirement of 200ns access time. password sector protection corrected 1 s (built-in delay for each password check) to 2 s. lock register command set definitions added new information for this section. password protection command set definitions added new information for this section. non-volatile sector protection command set definitions added new information for this section. global volatile sector protection freeze command set added new information for this section. volatile sector prot ection command set added new information for this section. secured silicon sector entry command added new information for this section. secured silicon sector exit command added new information for this section. ** - rysu 03/02/2004 a3:connection diagrams removed 56-pin reverse tsop diagram. ordering information updated the standard products for the s29gl512/256/128n devices and modified the valid combinations tables. word program command sequence added new information to this section. lock register command set definitions added new information to this section. table 13 updated this table. (continued) document title:s29gl512n , S29GL256N, s29gl128n 512, 256, 128 mbit, 3 v, page flash featuring 110 nm mirrorbit document number: 002-01522 rev. ecn no. orig. of change submission date description of change not recommended for new design
document number: 002-01522 rev. *b page 86 of 92 s29gl512n S29GL256N s29gl128n ** - rysu 05/13/2004 a4:global removed references to rtsop. distinctive characteristics removed 16-word/32-byte page r ead buffer from performance characteristics. changed low power consumption to 25 ma typical active read current and removed 10 ma typical intrapage active read current. ordering information changed formatting of pages. changed model numbers from 00,01,02,03 to 01, 02, v1, v2. table device bus operations combined wp# and acc columns. tables cfi query identification string, system interface string, device geometry definition, and primary vendor-specific extended query added address (x8) column. word program command sequence added text to fourth paragraph. figure write buffer programming operation added note references and removed dq15 and dq13. figure program susp end/program resume changed field to read xxxh/b0h and xxxh/30h. password protection command set definitions replaced all text. command definitions changed the first cycle address of cfi query to 55. memory array commands (x8) table changed the third cycle data device id to 90. removed unlock bypass reset. removed note 12 and 13. figure data# polling algorithm removed dq15 and dq13. absolute maximum ratings removed vcc from all other pins with respect to ground. cmos compatible changed the max of icc4 to 70 ma. added vil to the test conditio ns of icc5, icc6, and icc7 change the min of vil to - 0.1 v. updated note 5. read-only operations?s29gl128n only added tceh parameter to table.1/8/16 figure read operation timings added tceh to figure. (continued) document title:s29gl512n , S29GL256N, s29gl128n 512, 256, 128 mbit, 3 v, page flash featuring 110 nm mirrorbit document number: 002-01522 rev. ecn no. orig. of change submission date description of change not recommended for new design
document number: 002-01522 rev. *b page 87 of 92 s29gl512n S29GL256N s29gl128n ** - rysu 05/13/2004 figure page read timings change a1-a0 to a2-a0. erase and program operations updated twhwh1 and twhwh2 with values. figure chip/sector erase operation timings changed 5555h to 55h and 3030h to 30h. figure data# polling timings (during embedded algorithms) removed dq15 and dq14-dq8 added note 2 figure toggle bit timings (during embedded algorithms) changed dq6 & dq14/dq2 & dq10 to dq2 and dq6. alternate ce# controlled erase and program operations updated twhwh1 and twhwh2 with values. latchup characteristics removed table. erase and programming performance updated tbd with values. updated note 1 and 2. physical dimensions removed the reverse pinout information and note 3. ** - rysu 09/29/2004 a5:performance characteristics removed 80 ns. product selector guide updated values in tables. ordering information created a family table. operating ranges updated vio. cmos characteristics created a family table. read-only operations created a family table. hardware reset (reset#) created a family table. figure 13, ?reset timings,? added trh to waveform. erase and program operations created a family table. alternate ce# controlled erase and program operations created a family table. erase and programming performance created a family table. (continued) document title:s29gl512n , S29GL256N, s29gl128n 512, 256, 128 mbit, 3 v, page flash featuring 110 nm mirrorbit document number: 002-01522 rev. ecn no. orig. of change submission date description of change not recommended for new design
document number: 002-01522 rev. *b page 88 of 92 s29gl512n S29GL256N s29gl128n ** - rysu 01/24/2005 a6:global updated access times for s29gl512n. product selector guides all tables updated. valid combinations tables all tables updated. ac characteristics re ad-only options table added note for 90 ns speed options. ac characteristics erase and programming performance table added note for 90 ns speed options. figure data# polling timings (during embedded algorithms) updated timing diagram. ac characteristics alternate ce# controlled erase and program operations table added note for 90 ns speed options. ** - rysu 02/14/2005 a7:distinctive characteristics added product availability table ordering information under model numbers, changed vio voltage values for models v1 and v2. physical dimensions updated package table ** - rysu 05/09/2005 a8:product availability table updated data in vcc and availability columns. product selector guide combined gl128n and gl256n tables. changed upper limit of vio voltage range to 3.6 v. ordering information added wireless temperature range. co mbined valid combinations table and updated for wireless temperature range part numbers. dc characteristics table added vio = vcc test condition to icc4, icc5, icc6 specifications. corrected unit of measure on icc4 to a. changed maximum specifications for iacc (on acc pin) and icc3 to 90 ma. tables memory array commands (x16) to sector protection commands (x8), memory array and sector protection (x8 & x16) re-formatted command definition tables for easier reference. advance information on s9gl-p ac characteristics changed speed specifications and units of measure for tready, trp, trh, and trpd. changed specifications on tready from maximum to minimum. (continued) document title:s29gl512n , S29GL256N, s29gl128n 512, 256, 128 mbit, 3 v, page flash featuring 110 nm mirrorbit document number: 002-01522 rev. ecn no. orig. of change submission date description of change not recommended for new design
document number: 002-01522 rev. *b page 89 of 92 s29gl512n S29GL256N s29gl128n ** - rysu 06/15/2005 a9:ordering info rmation table added note to temperature range. valid combinations table replaced table. dc characteristics table replaced vil lines for icc4, icc5, icc6. connection diagrams modified 56-pin standard tsop. modified 64-ball fortified bga. advance information on s9gl-p ac characteristics added second table. (continued) document title:s29gl512n , S29GL256N, s29gl128n 512, 256, 128 mbit, 3 v, page flash featuring 110 nm mirrorbit document number: 002-01522 rev. ecn no. orig. of change submission date description of change not recommended for new design
document number: 002-01522 rev. *b page 90 of 92 s29gl512n S29GL256N s29gl128n ** - rysu 04/22/2006 b0:global changed document status to full production. ordering information changed description of ?a? for package materials set. modified s29gl128n valid combinations table. s29gl128n sector address table corrected bit range values for a22?a16. persistent protection bit (ppb) corrected typo in second sentence, second paragraph. secured silicon sector flash memory region deleted note at end of second paragraph. customer lockable: secured silicon sector not programmed or protected at the factory modified 1st bullet text. write protect (wp#) modified third paragraph. device geometry definition table changed 1st x8 address for erase block region 2. word program command sequence modified fourth paragraph. write buffer programming deleted note from eighth paragraph. program suspend/program resume command sequence corrected typos in first paragraph. lock register command set definitions modified fifth paragraph. volatile sector prot ection command set modified fourth paragraph. sector protection commands (x16) table changed read command address for lock register bits memory array commands (x8) added program and unlock bypass mode commands to table. write operation status deleted note (second paragraph). dc characteristics table modified test conditions for icc4. ** - rysu 05/05/2006 b1:ordering information modified speed option, package mate rial set, temperature range descriptions in breakout diagram. modified note 1. advance information on s29gl-p ac characteristics hardware reset (reset#) replaced contents in section. ** - rysu 10/03/2006 connection diagrams corrected 56-pin tsop package drawing. (continued) document title:s29gl512n , S29GL256N, s29gl128n 512, 256, 128 mbit, 3 v, page flash featuring 110 nm mirrorbit document number: 002-01522 rev. ecn no. orig. of change submission date description of change not recommended for new design
document number: 002-01522 rev. *b page 91 of 92 s29gl512n S29GL256N s29gl128n ** - rysu 01/19/2007 b4:global added obsolescence and migration notice. product selector guide changed manimum vio for vcc = 2.7? 3.6v and vio = 1.65 v minimum. ** - rysu 02/06/2007 b5:global revised obsolescence and migration notice. ** - rysu 11/08/2007 b6:advance information on s29gl-r 65nm mirrorbit hardware reset (reset#) and power-up sequence added advanced information ** - rysu 02/12/2008 b7:erase and programming performance chip program time: removed comment advance information on s29gl-r 65nm mirrorbit hardware reset (reset#) and power-up sequence power-up sequence timings table: reduced timing from 500 s to 300 s ** - rysu 04/22/2008 b8:end of life notice added ?retired product? status te xt to cover page, distinctive characteristics page and ordering information sections of data sheet. *a 5043543 rysu 12/11/2015 updated to cypress template *b 5074572 rysu 01/08/2016 updated the s uggested replacement parts in t he note in blue font in page 1. removed spansion revision history (continued) document title:s29gl512n , S29GL256N, s29gl128n 512, 256, 128 mbit, 3 v, page flash featuring 110 nm mirrorbit document number: 002-01522 rev. ecn no. orig. of change submission date description of change not recommended for new design
document number: 002-01522 rev. *b revised january 08, 2016 page 92 of 92 cypress ? , spansion ? , mirrorbit ? , mirrorbit ? eclipse?, ornand?, ecoram?, hyperbus?, hyperflash?, and combinations thereof, are trademarks and registered trademarks of cypr ess semiconductor corp. all products and company names mentioned in this document may be the trademarks of their respective holders . ? cypress semiconductor corporation, 2003-2016. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. s29gl512n S29GL256N s29gl128n sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representative s, and distributors. to find the office closest to you, visit us at cypress locations . products automotive........................... .......cypress.com/ go/automotive clocks & buffers ................................ cypress.com/go/clocks interface......................................... cypress.com/go/interface lighting & power control............ cypress.com/go/powerpsoc memory................................ ........... cypress.com/go/memory psoc ...................................... ..............cypress.com/go/psoc touch sensing ........................ ............ cypress.com/go/touch usb controllers....................................cypress.com/go/usb wireless/rf .................................... cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support not recommended for new design


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